From 6798cee2a53e9183c9202a5b3e6ee473c07d8470 Mon Sep 17 00:00:00 2001 From: Jordi Pakey-Rodriguez Date: Mon, 6 Mar 2017 16:06:52 -0600 Subject: [PATCH] stm32f2+: flash: Rename FLASH_ACR_XCE -> FLASH_ACR_XCEN Match the datasheet register names better. squish into xcev --- .../stm32/common/flash_common_f24.h | 5 ++- lib/stm32/common/flash_common_f24.c | 9 +++--- lib/stm32/f2/rcc.c | 2 +- lib/stm32/f4/rcc.c | 32 +++++++++---------- lib/stm32/f7/rcc.c | 2 +- 5 files changed, 24 insertions(+), 26 deletions(-) diff --git a/include/libopencm3/stm32/common/flash_common_f24.h b/include/libopencm3/stm32/common/flash_common_f24.h index 3548518a..e75f1445 100644 --- a/include/libopencm3/stm32/common/flash_common_f24.h +++ b/include/libopencm3/stm32/common/flash_common_f24.h @@ -51,8 +51,8 @@ #define FLASH_ACR_DCRST (1 << 12) #define FLASH_ACR_ICRST (1 << 11) -#define FLASH_ACR_DCE (1 << 10) -#define FLASH_ACR_ICE (1 << 9) +#define FLASH_ACR_DCEN (1 << 10) +#define FLASH_ACR_ICEN (1 << 9) #define FLASH_ACR_PRFTEN (1 << 8) /* --- FLASH_SR values ----------------------------------------------------- */ @@ -147,4 +147,3 @@ END_DECLS #warning "only via flash.h" #endif /** @endcond */ - diff --git a/lib/stm32/common/flash_common_f24.c b/lib/stm32/common/flash_common_f24.c index 1ca65786..4864bd6b 100644 --- a/lib/stm32/common/flash_common_f24.c +++ b/lib/stm32/common/flash_common_f24.c @@ -48,7 +48,7 @@ static inline void flash_set_program_size(uint32_t psize) void flash_dcache_enable(void) { - FLASH_ACR |= FLASH_ACR_DCE; + FLASH_ACR |= FLASH_ACR_DCEN; } /*---------------------------------------------------------------------------*/ @@ -58,7 +58,7 @@ void flash_dcache_enable(void) void flash_dcache_disable(void) { - FLASH_ACR &= ~FLASH_ACR_DCE; + FLASH_ACR &= ~FLASH_ACR_DCEN; } /*---------------------------------------------------------------------------*/ @@ -68,7 +68,7 @@ void flash_dcache_disable(void) void flash_icache_enable(void) { - FLASH_ACR |= FLASH_ACR_ICE; + FLASH_ACR |= FLASH_ACR_ICEN; } /*---------------------------------------------------------------------------*/ @@ -78,7 +78,7 @@ void flash_icache_enable(void) void flash_icache_disable(void) { - FLASH_ACR &= ~FLASH_ACR_ICE; + FLASH_ACR &= ~FLASH_ACR_ICEN; } /*---------------------------------------------------------------------------*/ @@ -412,4 +412,3 @@ void flash_program_option_bytes(uint32_t data) flash_wait_for_last_operation(); } /**@}*/ - diff --git a/lib/stm32/f2/rcc.c b/lib/stm32/f2/rcc.c index 999dc116..ff3a4a8a 100644 --- a/lib/stm32/f2/rcc.c +++ b/lib/stm32/f2/rcc.c @@ -57,7 +57,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .apb1_frequency = 30000000, .apb2_frequency = 60000000, diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c index b4098c55..eb30dd25 100644 --- a/lib/stm32/f4/rcc.c +++ b/lib/stm32/f4/rcc.c @@ -60,7 +60,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 48000000, .apb1_frequency = 12000000, @@ -75,7 +75,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, .ahb_frequency = 84000000, .apb1_frequency = 42000000, @@ -91,7 +91,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 120000000, .apb1_frequency = 30000000, @@ -106,7 +106,7 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, .ahb_frequency = 168000000, .apb1_frequency = 42000000, @@ -125,7 +125,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 48000000, .apb1_frequency = 12000000, @@ -140,7 +140,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, .ahb_frequency = 84000000, .apb1_frequency = 42000000, @@ -156,7 +156,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 120000000, .apb1_frequency = 30000000, @@ -171,7 +171,7 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, .ahb_frequency = 168000000, .apb1_frequency = 42000000, @@ -190,7 +190,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 48000000, .apb1_frequency = 12000000, @@ -205,7 +205,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, .ahb_frequency = 84000000, .apb1_frequency = 42000000, @@ -221,7 +221,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 120000000, .apb1_frequency = 30000000, @@ -236,7 +236,7 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, .ahb_frequency = 168000000, .apb1_frequency = 42000000, @@ -255,7 +255,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 48000000, .apb1_frequency = 12000000, @@ -270,7 +270,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_2, .ppre2 = RCC_CFGR_PPRE_DIV_NONE, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_2WS, .ahb_frequency = 84000000, .apb1_frequency = 42000000, @@ -286,7 +286,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, .power_save = 1, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_3WS, .ahb_frequency = 120000000, .apb1_frequency = 30000000, @@ -301,7 +301,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_LATENCY_5WS, .ahb_frequency = 168000000, .apb1_frequency = 42000000, diff --git a/lib/stm32/f7/rcc.c b/lib/stm32/f7/rcc.c index a63cf1b6..3de4762c 100644 --- a/lib/stm32/f7/rcc.c +++ b/lib/stm32/f7/rcc.c @@ -15,7 +15,7 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = { .hpre = RCC_CFGR_HPRE_DIV_NONE, .ppre1 = RCC_CFGR_PPRE_DIV_4, .ppre2 = RCC_CFGR_PPRE_DIV_2, - .flash_config = FLASH_ACR_ICE | FLASH_ACR_DCE | + .flash_config = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_7WS, .apb1_frequency = 108000000, .apb2_frequency = 216000000,