swm050: register fix for timer_clock_div
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@ -187,7 +187,7 @@ void timer_clock_div(uint8_t div)
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/* If the value is 0 or 1, make it odd, meaning no divide. */
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/* If the value is 0 or 1, make it odd, meaning no divide. */
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/* Otherwise, drop div to the closest even value. */
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/* Otherwise, drop div to the closest even value. */
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div = (div <= 1) ? 1 : (div & ~0x1);
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div = (div <= 1) ? 1 : (div & ~0x1);
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SYSCTL_SYS_CFG_1 = (~TIMER_DIV_MASK & SYSCTL_SYS_CFG_1) | (div << 16);
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SYSCTL_SYS_CFG_0 = (~TIMER_DIV_MASK & SYSCTL_SYS_CFG_0) | (div << 16);
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}
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}
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/**
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/**
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