stm32f7: enable fsmc
This uses the existing f4 code as a new shared common base code.
This commit is contained in:
Oliver Meier
Karl Palsson
parent
4fc7196463
commit
16cfc6d848
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/** @addtogroup fmc_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2013
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* Chuck McManis <cmcmanis@mcmanis.com>
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*
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* @date 2013
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*
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* This library supports the Flexible Memory Controller (FMC) in the STM32F4xx
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* and STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_FMC_COMMON_F47_H
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#define LIBOPENCM3_FMC_COMMON_F47_H
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#ifndef LIBOPENCM3_FSMC_H
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#error "This file should not be included directly, it is included with fsmc.h"
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#endif
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/* --- Convenience macros -------------------------------------------------- */
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#define FMC_BANK5_BASE 0xa0000000U
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#define FMC_BANK6_BASE 0xb0000000U
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#define FMC_BANK7_BASE 0xc0000000U
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#define FMC_BANK8_BASE 0xd0000000U
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/* --- FMC registers ------------------------------------------------------ */
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/* SDRAM Control Registers 1 .. 2 */
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#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x))
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#define FMC_SDCR1 FMC_SDCR(0)
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#define FMC_SDCR2 FMC_SDCR(1)
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/* SDRAM Timing Registers 1 .. 2 */
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#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x))
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#define FMC_SDTR1 FMC_SDTR(0)
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#define FMC_SDTR2 FMC_SDTR(1)
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/* SDRAM Command Mode Register */
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#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150)
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/* SDRAM Refresh Timer Register */
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#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154)
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/* SDRAM Status Register */
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#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158)
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/* --- FMC_SDCRx values ---------------------------------------------------- */
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/* Bits [31:15]: Reserved. */
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/* RPIPE: Read Pipe */
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#define FMC_SDCR_RPIPE_SHIFT 13
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#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT)
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/* RBURST: Burst Read */
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#define FMC_SDCR_RBURST (1 << 12)
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/* SDCLK: SDRAM Clock Configuration */
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#define FMC_SDCR_SDCLK_SHIFT 10
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#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT)
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/* WP: Write Protect */
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#define FMC_SDCR_WP_ENABLE (1 << 9)
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/* CAS: CAS Latency */
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#define FMC_SDCR_CAS_SHIFT 7
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#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT)
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#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT)
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#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT)
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/* NB: Number of Internal banks */
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#define FMC_SDCR_NB2 0
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#define FMC_SDCR_NB4 (1 << 6)
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/* MWID: Memory width */
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#define FMC_SDCR_MWID_SHIFT 4
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#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT)
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#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT)
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#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT)
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/* NR: Number of rows */
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#define FMC_SDCR_NR_SHIFT 2
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#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT)
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#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT)
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#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT)
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/* NC: Number of Columns */
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#define FMC_SDCR_NC_SHIFT 0
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#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT)
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/* --- FMC_SDTRx values --------------------------------------------------- */
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/* Bits [31:28]: Reserved. */
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/* TRCD: Row to Column Delay */
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#define FMC_SDTR_TRCD_SHIFT 24
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#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT)
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/* TRP: Row Precharge Delay */
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#define FMC_SDTR_TRP_SHIFT 20
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#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT)
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/* TWR: Recovery Delay */
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#define FMC_SDTR_TWR_SHIFT 16
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#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT)
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/* TRC: Row Cycle Delay */
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#define FMC_SDTR_TRC_SHIFT 12
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#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT)
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/* TRAS: Self Refresh Time */
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#define FMC_SDTR_TRAS_SHIFT 8
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#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT)
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/* TXSR: Exit Self-refresh Delay */
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#define FMC_SDTR_TXSR_SHIFT 4
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#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT)
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/* TRMD: Load Mode Register to Active */
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#define FMC_SDTR_TMRD_SHIFT 0
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#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT)
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/*
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* Some config bits only count in CR1 or TR1, even if you
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* are just configuring bank 2, so these masks let you copy
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* out those bits after you have computed values for CR2 and
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* TR2 and put them into CR1 and TR1
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*/
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#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK)
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#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \
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FMC_SDCR_RPIPE_MASK | \
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FMC_SDCR_RBURST)
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/* --- FMC_SDCMR values --------------------------------------------------- */
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/* Bits [31:22]: Reserved. */
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/* MRD: Mode Register Definition */
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#define FMC_SDCMR_MRD_SHIFT 9
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#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT)
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/* NRFS: Number of Auto-refresh */
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#define FMC_SDCMR_NRFS_SHIFT 5
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#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT)
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/* CTB1: Command Target Bank 1 */
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#define FMC_SDCMR_CTB1 (1 << 4)
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/* CTB2: Command Target Bank 2 */
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#define FMC_SDCMR_CTB2 (1 << 3)
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/* MODE: Command Mode */
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#define FMC_SDCMR_MODE_SHIFT 0
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#define FMC_SDCMR_MODE_MASK 7
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#define FMC_SDCMR_MODE_NORMAL 0
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#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1
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#define FMC_SDCMR_MODE_PALL 2
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#define FMC_SDCMR_MODE_AUTO_REFRESH 3
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#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4
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#define FMC_SDCMR_MODE_SELF_REFRESH 5
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#define FMC_SDCMR_MODE_POWER_DOWN 6
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/* --- FMC_SDRTR values ---------------------------------------------------- */
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/* Bits [31:15]: Reserved. */
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/* REIE: Refresh Error Interrupt Enable */
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#define FMC_SDRTR_REIE (1 << 14)
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/* COUNT: Refresh Timer Count */
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#define FMC_SDRTR_COUNT_SHIFT 1
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#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT)
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/* CRE: Clear Refresh Error Flag */
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#define FMC_SDRTR_CRE (1 << 0)
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/* --- FMC_SDSR values ---------------------------------------------------- */
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/* Bits [31:6]: Reserved. */
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/* BUSY: Set if the SDRAM is working on the command */
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#define FMC_SDSR_BUSY (1 << 5)
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/* MODES: Status modes */
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#define FMC_SDSR_MODE_NORMAL 0
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#define FMC_SDSR_MODE_SELF_REFRESH 1
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#define FMC_SDSR_MODE_POWER_DOWN 2
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/* Mode shift */
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#define FMC_SDSR_MODE2_SHIFT 3
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#define FMC_SDSR_MODE1_SHIFT 1
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/* RE: Refresh Error */
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#define FMC_SDSR_RE (1 << 0)
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/* Helper function for setting the timing parameters */
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struct sdram_timing {
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int trcd; /* RCD Delay */
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int trp; /* RP Delay */
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int twr; /* Write Recovery Time */
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int trc; /* Row Cycle Delay */
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int tras; /* Self Refresh TIme */
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int txsr; /* Exit Self Refresh Time */
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int tmrd; /* Load to Active delay */
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};
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/* Mode register parameters */
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#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS };
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enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL,
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SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE,
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SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN };
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/* Send an array of timing parameters (indices above) to create SDTR register
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* value
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*/
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BEGIN_DECLS
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uint32_t sdram_timing(struct sdram_timing *t);
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void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd,
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int autorefresh, int modereg);
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END_DECLS
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#endif
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/**@}*/
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@ -1,8 +1,11 @@
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/** @defgroup fmc_defines FMC Defines
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* @brief <b>Defined Constants and Types for the STM32F4xx Flexible Memory
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* Controller</b>
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* @ingroup STM32F4xx_defines
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Chuck McManis <cmcmanis@mcmanis.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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@ -16,239 +19,17 @@
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#ifndef LIBOPENCM3_FMC_H
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#define LIBOPENCM3_FMC_H
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#ifndef LIBOPENCM3_F4_FMC_H
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#define LIBOPENCM3_F4_FMC_H
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#ifndef LIBOPENCM3_FSMC_H
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error "This file should not be included directly, it is included with fsmc.h"
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#error "This file should not be included directly, it is included with fsmc.h"
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#endif
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/* --- Convenience macros -------------------------------------------------- */
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#define FMC_BANK5_BASE 0xa0000000U
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#define FMC_BANK6_BASE 0xb0000000U
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#define FMC_BANK7_BASE 0xc0000000U
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#define FMC_BANK8_BASE 0xd0000000U
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/* --- FMC registers ------------------------------------------------------ */
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/* SDRAM Control Registers 1 .. 2 */
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#define FMC_SDCR(x) MMIO32(FSMC_BASE + 0x140 + 4 * (x))
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#define FMC_SDCR1 FMC_SDCR(0)
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#define FMC_SDCR2 FMC_SDCR(1)
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/* SDRAM Timing Registers 1 .. 2 */
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#define FMC_SDTR(x) MMIO32(FSMC_BASE + 0x148 + 4 * (x))
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#define FMC_SDTR1 FMC_SDTR(0)
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#define FMC_SDTR2 FMC_SDTR(1)
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/* SDRAM Command Mode Register */
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#define FMC_SDCMR MMIO32(FSMC_BASE + (uint32_t) 0x150)
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/* SDRAM Refresh Timer Register */
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#define FMC_SDRTR MMIO32(FSMC_BASE + 0x154)
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/* SDRAM Status Register */
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#define FMC_SDSR MMIO32(FSMC_BASE + (uint32_t) 0x158)
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/* --- FMC_SDCRx values ---------------------------------------------------- */
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/* Bits [31:15]: Reserved. */
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/* RPIPE: Read Pipe */
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#define FMC_SDCR_RPIPE_SHIFT 13
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#define FMC_SDCR_RPIPE_MASK (3 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_NONE (0 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_1CLK (1 << FMC_SDCR_RPIPE_SHIFT)
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#define FMC_SDCR_RPIPE_2CLK (2 << FMC_SDCR_RPIPE_SHIFT)
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/* RBURST: Burst Read */
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#define FMC_SDCR_RBURST (1 << 12)
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/* SDCLK: SDRAM Clock Configuration */
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#define FMC_SDCR_SDCLK_SHIFT 10
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#define FMC_SDCR_SDCLK_MASK (3 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_DISABLE (0 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_2HCLK (2 << FMC_SDCR_SDCLK_SHIFT)
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#define FMC_SDCR_SDCLK_3HCLK (3 << FMC_SDCR_SDCLK_SHIFT)
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/* WP: Write Protect */
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#define FMC_SDCR_WP_ENABLE (1 << 9)
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/* CAS: CAS Latency */
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#define FMC_SDCR_CAS_SHIFT 7
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#define FMC_SDCR_CAS_1CYC (1 << FMC_SDCR_CAS_SHIFT)
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#define FMC_SDCR_CAS_2CYC (2 << FMC_SDCR_CAS_SHIFT)
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#define FMC_SDCR_CAS_3CYC (3 << FMC_SDCR_CAS_SHIFT)
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/* NB: Number of Internal banks */
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#define FMC_SDCR_NB2 0
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#define FMC_SDCR_NB4 (1 << 6)
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/* MWID: Memory width */
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#define FMC_SDCR_MWID_SHIFT 4
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#define FMC_SDCR_MWID_8b (0 << FMC_SDCR_MWID_SHIFT)
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#define FMC_SDCR_MWID_16b (1 << FMC_SDCR_MWID_SHIFT)
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#define FMC_SDCR_MWID_32b (2 << FMC_SDCR_MWID_SHIFT)
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/* NR: Number of rows */
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#define FMC_SDCR_NR_SHIFT 2
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#define FMC_SDCR_NR_11 (0 << FMC_SDCR_NR_SHIFT)
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#define FMC_SDCR_NR_12 (1 << FMC_SDCR_NR_SHIFT)
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#define FMC_SDCR_NR_13 (2 << FMC_SDCR_NR_SHIFT)
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/* NC: Number of Columns */
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#define FMC_SDCR_NC_SHIFT 0
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#define FMC_SDCR_NC_8 (0 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_9 (1 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_10 (2 << FMC_SDCR_NC_SHIFT)
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#define FMC_SDCR_NC_11 (3 << FMC_SDCR_NC_SHIFT)
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/* --- FMC_SDTRx values --------------------------------------------------- */
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/* Bits [31:28]: Reserved. */
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/* TRCD: Row to Column Delay */
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#define FMC_SDTR_TRCD_SHIFT 24
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#define FMC_SDTR_TRCD_MASK (15 << FMC_SDTR_TRCD_SHIFT)
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/* TRP: Row Precharge Delay */
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#define FMC_SDTR_TRP_SHIFT 20
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#define FMC_SDTR_TRP_MASK (15 << FMC_SDTR_TRP_SHIFT)
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/* TWR: Recovery Delay */
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#define FMC_SDTR_TWR_SHIFT 16
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#define FMC_SDTR_TWR_MASK (15 << FMC_SDTR_TWR_SHIFT)
|
||||
|
||||
/* TRC: Row Cycle Delay */
|
||||
#define FMC_SDTR_TRC_SHIFT 12
|
||||
#define FMC_SDTR_TRC_MASK (15 << FMC_SDTR_TRC_SHIFT)
|
||||
|
||||
/* TRAS: Self Refresh Time */
|
||||
#define FMC_SDTR_TRAS_SHIFT 8
|
||||
#define FMC_SDTR_TRAS_MASK (15 << FMC_SDTR_TRAS_SHIFT)
|
||||
|
||||
/* TXSR: Exit Self-refresh Delay */
|
||||
#define FMC_SDTR_TXSR_SHIFT 4
|
||||
#define FMC_SDTR_TXSR_MASK (15 << FMC_SDTR_TXSR_SHIFT)
|
||||
|
||||
/* TRMD: Load Mode Register to Active */
|
||||
#define FMC_SDTR_TMRD_SHIFT 0
|
||||
#define FMC_SDTR_TMRD_MASK (15 << FMC_SDTR_TMRD_SHIFT)
|
||||
|
||||
/*
|
||||
* Some config bits only count in CR1 or TR1, even if you
|
||||
* are just configuring bank 2, so these masks let you copy
|
||||
* out those bits after you have computed values for CR2 and
|
||||
* TR2 and put them into CR1 and TR1
|
||||
*/
|
||||
#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK)
|
||||
#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \
|
||||
FMC_SDCR_RPIPE_MASK | \
|
||||
FMC_SDCR_RBURST)
|
||||
|
||||
/* --- FMC_SDCMR values --------------------------------------------------- */
|
||||
|
||||
/* Bits [31:22]: Reserved. */
|
||||
|
||||
/* MRD: Mode Register Definition */
|
||||
#define FMC_SDCMR_MRD_SHIFT 9
|
||||
#define FMC_SDCMR_MRD_MASK (0x1fff << FMC_SDCMR_MRD_SHIFT)
|
||||
|
||||
/* NRFS: Number of Auto-refresh */
|
||||
#define FMC_SDCMR_NRFS_SHIFT 5
|
||||
#define FMC_SDCMR_NRFS_MASK (15 << FMC_SDCMR_NRFS_SHIFT)
|
||||
|
||||
/* CTB1: Command Target Bank 1 */
|
||||
#define FMC_SDCMR_CTB1 (1 << 4)
|
||||
|
||||
/* CTB2: Command Target Bank 2 */
|
||||
#define FMC_SDCMR_CTB2 (1 << 3)
|
||||
|
||||
/* MODE: Command Mode */
|
||||
#define FMC_SDCMR_MODE_SHIFT 0
|
||||
#define FMC_SDCMR_MODE_MASK 7
|
||||
#define FMC_SDCMR_MODE_NORMAL 0
|
||||
#define FMC_SDCMR_MODE_CLOCK_CONFIG_ENA 1
|
||||
#define FMC_SDCMR_MODE_PALL 2
|
||||
#define FMC_SDCMR_MODE_AUTO_REFRESH 3
|
||||
#define FMC_SDCMR_MODE_LOAD_MODE_REGISTER 4
|
||||
#define FMC_SDCMR_MODE_SELF_REFRESH 5
|
||||
#define FMC_SDCMR_MODE_POWER_DOWN 6
|
||||
|
||||
/* --- FMC_SDRTR values ---------------------------------------------------- */
|
||||
|
||||
/* Bits [31:15]: Reserved. */
|
||||
|
||||
/* REIE: Refresh Error Interrupt Enable */
|
||||
#define FMC_SDRTR_REIE (1 << 14)
|
||||
|
||||
/* COUNT: Refresh Timer Count */
|
||||
#define FMC_SDRTR_COUNT_SHIFT 1
|
||||
#define FMC_SDRTR_COUNT_MASK (0x1fff << FMC_SDRTR_COUNT_SHIFT)
|
||||
|
||||
/* CRE: Clear Refresh Error Flag */
|
||||
#define FMC_SDRTR_CRE (1 << 0)
|
||||
|
||||
/* --- FMC_SDSR values ---------------------------------------------------- */
|
||||
|
||||
/* Bits [31:6]: Reserved. */
|
||||
|
||||
/* BUSY: Set if the SDRAM is working on the command */
|
||||
#define FMC_SDSR_BUSY (1 << 5)
|
||||
|
||||
/* MODES: Status modes */
|
||||
#define FMC_SDSR_MODE_NORMAL 0
|
||||
#define FMC_SDSR_MODE_SELF_REFRESH 1
|
||||
#define FMC_SDSR_MODE_POWER_DOWN 2
|
||||
|
||||
/* Mode shift */
|
||||
#define FMC_SDSR_MODE2_SHIFT 3
|
||||
#define FMC_SDSR_MODE1_SHIFT 1
|
||||
|
||||
/* RE: Refresh Error */
|
||||
#define FMC_SDSR_RE (1 << 0)
|
||||
|
||||
/* Helper function for setting the timing parameters */
|
||||
struct sdram_timing {
|
||||
int trcd; /* RCD Delay */
|
||||
int trp; /* RP Delay */
|
||||
int twr; /* Write Recovery Time */
|
||||
int trc; /* Row Cycle Delay */
|
||||
int tras; /* Self Refresh TIme */
|
||||
int txsr; /* Exit Self Refresh Time */
|
||||
int tmrd; /* Load to Active delay */
|
||||
};
|
||||
|
||||
/* Mode register parameters */
|
||||
#define SDRAM_MODE_BURST_LENGTH_1 ((uint16_t)0x0000)
|
||||
#define SDRAM_MODE_BURST_LENGTH_2 ((uint16_t)0x0001)
|
||||
#define SDRAM_MODE_BURST_LENGTH_4 ((uint16_t)0x0002)
|
||||
#define SDRAM_MODE_BURST_LENGTH_8 ((uint16_t)0x0004)
|
||||
#define SDRAM_MODE_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
|
||||
#define SDRAM_MODE_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
|
||||
#define SDRAM_MODE_CAS_LATENCY_2 ((uint16_t)0x0020)
|
||||
#define SDRAM_MODE_CAS_LATENCY_3 ((uint16_t)0x0030)
|
||||
#define SDRAM_MODE_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
|
||||
#define SDRAM_MODE_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
|
||||
#define SDRAM_MODE_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
|
||||
|
||||
enum fmc_sdram_bank { SDRAM_BANK1, SDRAM_BANK2, SDRAM_BOTH_BANKS };
|
||||
enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL,
|
||||
SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE,
|
||||
SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN };
|
||||
|
||||
/* Send an array of timing parameters (indices above) to create SDTR register
|
||||
* value
|
||||
*/
|
||||
BEGIN_DECLS
|
||||
|
||||
uint32_t sdram_timing(struct sdram_timing *t);
|
||||
void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd,
|
||||
int autorefresh, int modereg);
|
||||
|
||||
END_DECLS
|
||||
#include <libopencm3/stm32/common/fmc_common_f47.h>
|
||||
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
|
|
|
|||
|
|
@ -0,0 +1,38 @@
|
|||
/** @defgroup fmc_defines FMC Defines
|
||||
* @brief <b>Defined Constants and Types for the STM32F7xx Flexible Memory
|
||||
* Controller</b>
|
||||
* @ingroup STM32F7xx_defines
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/**@{*/
|
||||
|
||||
#ifndef LIBOPENCM3_F7_FMC_H
|
||||
#define LIBOPENCM3_F7_FMC_H
|
||||
|
||||
#ifndef LIBOPENCM3_FSMC_H
|
||||
#error "This file should not be included directly, it is included with fsmc.h"
|
||||
#endif
|
||||
|
||||
#include <libopencm3/stm32/common/fmc_common_f47.h>
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
#define FSMC_BASE FMCC_BASE
|
||||
|
||||
#endif
|
||||
|
||||
/**@}*/
|
||||
|
|
@ -23,16 +23,17 @@
|
|||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
|
||||
#if defined(STM32F4)
|
||||
#if defined(STM32F4)
|
||||
# include <libopencm3/stm32/f4/fmc.h>
|
||||
#elif defined(STM32F7)
|
||||
# include <libopencm3/stm32/f7/fmc.h>
|
||||
#endif
|
||||
|
||||
/* --- Convenience macros -------------------------------------------------- */
|
||||
|
||||
#define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */
|
||||
#define FSMC_BANK2_BASE 0x70000000U /* NAND flash */
|
||||
#define FSMC_BANK2_BASE 0x70000000U /* NAND flash (reserved in F7) */
|
||||
#define FSMC_BANK3_BASE 0x80000000U /* NAND flash */
|
||||
#define FSMC_BANK4_BASE 0x90000000U /* PC card */
|
||||
#define FSMC_BANK4_BASE 0x90000000U /* PC card (reserved in F7) */
|
||||
|
||||
/* --- FSMC registers ------------------------------------------------------ */
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,11 @@
|
|||
/** @addtogroup fmc_file FMC peripheral API
|
||||
@ingroup peripheral_apis
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
|
||||
|
||||
This library supports the Flexible Memory Controller in the STM32F4xx and
|
||||
STM32F7xx series of ARM Cortex Microcontrollers by ST Microelectronics.
|
||||
*/
|
||||
/*
|
||||
*
|
||||
* This file is part of the libopencm3 project.
|
||||
|
|
@ -21,6 +29,8 @@
|
|||
#include <stdint.h>
|
||||
#include <libopencm3/stm32/fsmc.h>
|
||||
|
||||
/**@{*/
|
||||
|
||||
/*
|
||||
* Install various timing values into the correct place in the
|
||||
* SDRAM Timing Control Register format.
|
||||
|
|
@ -97,3 +107,5 @@ sdram_command(enum fmc_sdram_bank bank,
|
|||
/* Send the next command */
|
||||
FMC_SDCMR = tmp_reg;
|
||||
}
|
||||
|
||||
/**@}*/
|
||||
|
|
@ -49,7 +49,7 @@ OBJS += dma_common_f24.o
|
|||
OBJS += exti_common_all.o
|
||||
OBJS += flash.o flash_common_all.o flash_common_f.o flash_common_f24.o
|
||||
OBJS += flash_common_idcache.o
|
||||
OBJS += fmc.o
|
||||
OBJS += fmc_common_f47.o
|
||||
OBJS += gpio_common_all.o gpio_common_f0234.o gpio.o
|
||||
OBJS += hash_common_f24.o
|
||||
OBJS += i2c_common_v1.o
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ OBJS += desig.o
|
|||
OBJS += dma_common_f24.o
|
||||
OBJS += exti_common_all.o
|
||||
OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o flash.o
|
||||
OBJS += fmc_common_f47.o
|
||||
OBJS += gpio.o gpio_common_all.o gpio_common_f0234.o
|
||||
OBJS += i2c_common_v2.o
|
||||
OBJS += iwdg_common_all.o
|
||||
|
|
|
|||
Loading…
Reference in New Issue