310 lines
9.0 KiB
C
310 lines
9.0 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_FSMC_H
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#define LIBOPENCM3_FSMC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/stm32/memorymap.h>
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#if defined(STM32F4)
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# include <libopencm3/stm32/f4/fmc.h>
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#elif defined(STM32F7)
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# include <libopencm3/stm32/f7/fmc.h>
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#endif
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/* --- Convenience macros -------------------------------------------------- */
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#define FSMC_BANK1_BASE 0x60000000U /* NOR / PSRAM */
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#define FSMC_BANK2_BASE 0x70000000U /* NAND flash (reserved in F7) */
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#define FSMC_BANK3_BASE 0x80000000U /* NAND flash */
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#define FSMC_BANK4_BASE 0x90000000U /* PC card (reserved in F7) */
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/* --- FSMC registers ------------------------------------------------------ */
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/* SRAM/NOR-Flash chip-select control registers 1..4 (FSMC_BCRx) */
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#define FSMC_BCR(x) MMIO32(FSMC_BASE + 0x00 + 8 * (x))
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#define FSMC_BCR1 FSMC_BCR(0)
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#define FSMC_BCR2 FSMC_BCR(1)
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#define FSMC_BCR3 FSMC_BCR(2)
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#define FSMC_BCR4 FSMC_BCR(3)
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/* SRAM/NOR-Flash chip-select timing registers 1..4 (FSMC_BTRx) */
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#define FSMC_BTR(x) MMIO32(FSMC_BASE + 0x04 + 8 * (x))
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#define FSMC_BTR1 FSMC_BTR(0)
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#define FSMC_BTR2 FSMC_BTR(1)
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#define FSMC_BTR3 FSMC_BTR(2)
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#define FSMC_BTR4 FSMC_BTR(3)
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/* SRAM/NOR-Flash write timing registers 1..4 (FSMC_BWTRx) */
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#define FSMC_BWTR(x) MMIO32(FSMC_BASE + 0x104 + 8 * (x))
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#define FSMC_BWTR1 FSMC_BWTR(0)
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#define FSMC_BWTR2 FSMC_BWTR(1)
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#define FSMC_BWTR3 FSMC_BWTR(2)
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#define FSMC_BWTR4 FSMC_BWTR(3)
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/* PC Card/NAND Flash control registers 2..4 (FSMC_PCRx) */
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#define FSMC_PCR(x) MMIO32(FSMC_BASE + 0x40 + 0x20 * (x))
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#define FSMC_PCR2 FSMC_PCR(1)
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#define FSMC_PCR3 FSMC_PCR(2)
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#define FSMC_PCR4 FSMC_PCR(3)
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/* FIFO status and interrupt registers 2..4 (FSMC_SRx) */
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#define FSMC_SR(x) MMIO32(FSMC_BASE + 0x44 + 0x20 * (x))
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#define FSMC_SR2 FSMC_SR(1)
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#define FSMC_SR3 FSMC_SR(2)
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#define FSMC_SR4 FSMC_SR(3)
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/* Common memory space timing registers 2..4 (FSMC_PMEMx) */
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#define FSMC_PMEM(x) MMIO32(FSMC_BASE + 0x48 + 0x20 * (x))
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#define FSMC_PMEM2 FSMC_PMEM(1)
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#define FSMC_PMEM3 FSMC_PMEM(2)
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#define FSMC_PMEM4 FSMC_PMEM(3)
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/* Attribute memory space timing registers 2..4 (FSMC_PATTx) */
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#define FSMC_PATT(x) MMIO32(FSMC_BASE + 0x4c + 0x20 * (x))
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#define FSMC_PATT2 FSMC_PATT(1)
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#define FSMC_PATT3 FSMC_PATT(2)
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#define FSMC_PATT4 FSMC_PATT(3)
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/* I/O space timing register 4 (FSMC_PIO4) */
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#define FSMC_PIO4 MMIO32(FSMC_BASE + 0xb0)
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/* ECC result registers 2/3 (FSMC_ECCRx) */
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#define FSMC_ECCR(x) MMIO32(FSMC_BASE + 0x54 + 0x20 * (x))
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#define FSMC_ECCR2 FSMC_ECCR(1)
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#define FSMC_ECCR3 FSMC_ECCR(2)
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/* --- FSMC_BCRx values ---------------------------------------------------- */
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/* Bits [31:20]: Reserved. */
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/* CBURSTRW: Write burst enable */
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#define FSMC_BCR_CBURSTRW (1 << 19)
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/* Bits [18:16]: Reserved. */
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/* ASYNCWAIT: Wait signal during asynchronous transfers */
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#define FSMC_BCR_ASYNCWAIT (1 << 15)
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/* EXTMOD: Extended mode enable */
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#define FSMC_BCR_EXTMOD (1 << 14)
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/* WAITEN: Wait enable bit */
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#define FSMC_BCR_WAITEN (1 << 13)
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/* WREN: Write enable bit */
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#define FSMC_BCR_WREN (1 << 12)
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/* WAITCFG: Wait timing configuration */
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#define FSMC_BCR_WAITCFG (1 << 11)
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/* WRAPMOD: Wrapped burst mode support */
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#define FSMC_BCR_WRAPMOD (1 << 10)
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/* WAITPOL: Wait signal polarity bit */
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#define FSMC_BCR_WAITPOL (1 << 9)
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/* BURSTEN: Burst enable bit */
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#define FSMC_BCR_BURSTEN (1 << 8)
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/* Bit 7: Reserved. */
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/* FACCEN: Flash access enable */
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#define FSMC_BCR_FACCEN (1 << 6)
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/* MWID[5:4]: Memory data bus width */
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#define FSMC_BCR_MWID (1 << 4)
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/* MTYP[3:2]: Memory type */
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#define FSMC_BCR_MTYP (1 << 2)
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/* MUXEN: Address/data multiplexing enable bit */
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#define FSMC_BCR_MUXEN (1 << 1)
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/* MBKEN: Memory bank enable bit */
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#define FSMC_BCR_MBKEN (1 << 0)
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/* --- FSMC_BTRx values ---------------------------------------------------- */
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/* Bits [31:30]: Reserved. */
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/* Same for read and write */
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#define FSMC_BTx_ACCMOD_A (0)
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#define FSMC_BTx_ACCMOD_B (1)
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#define FSMC_BTx_ACCMOD_C (2)
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#define FSMC_BTx_ACCMOD_D (3)
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/* ACCMOD[29:28]: Access mode */
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#define FSMC_BTR_ACCMOD (1 << 28)
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#define FSMC_BTR_ACCMODx(x) (((x) & 0x03) << 28)
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/* DATLAT[27:24]: Data latency (for synchronous burst NOR flash) */
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#define FSMC_BTR_DATLAT (1 << 24)
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#define FSMC_BTR_DATLATx(x) (((x) & 0x0f) << 24)
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/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
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#define FSMC_BTR_CLKDIV (1 << 20)
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#define FSMC_BTR_CLKDIVx(x) (((x) & 0x0f) << 20)
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/* BUSTURN[19:16]: Bus turnaround phase duration */
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#define FSMC_BTR_BUSTURN (1 << 16)
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#define FSMC_BTR_BUSTURNx(x) (((x) & 0x0f) << 16)
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/* DATAST[15:8]: Data-phase duration */
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#define FSMC_BTR_DATAST (1 << 8)
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#define FSMC_BTR_DATASTx(x) (((x) & 0xff) << 8)
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/* ADDHLD[7:4]: Address-hold phase duration */
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#define FSMC_BTR_ADDHLD (1 << 4)
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#define FSMC_BTR_ADDHLDx(x) (((x) & 0x0f) << 4)
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/* ADDSET[3:0]: Address setup phase duration */
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#define FSMC_BTR_ADDSET (1 << 0)
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#define FSMC_BTR_ADDSETx(x) (((x) & 0x0f) << 0)
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/* --- FSMC_BWTRx values --------------------------------------------------- */
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/* Bits [31:30]: Reserved. */
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/* ACCMOD[29:28]: Access mode */
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#define FSMC_BWTR_ACCMOD (1 << 28)
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/* DATLAT[27:24]: Data latency (for synchronous burst NOR Flash) */
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#define FSMC_BWTR_DATLAT (1 << 24)
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/* CLKDIV[23:20]: Clock divide ratio (for CLK signal) */
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#define FSMC_BWTR_CLKDIV (1 << 20)
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/* Bits [19..16]: Reserved. */
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/* DATAST[15:8]: Data-phase duration */
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#define FSMC_BWTR_DATAST (1 << 8)
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/* ADDHLD[7:4]: Address-hold phase duration */
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#define FSMC_BWTR_ADDHLD (1 << 4)
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/* ADDSET[3:0]: Address setup phase duration */
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#define FSMC_BWTR_ADDSET (1 << 0)
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/* --- FSMC_PCRx values ---------------------------------------------------- */
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/* Bits [31:20]: Reserved. */
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/* ECCPS[19:17]: ECC page size */
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#define FSMC_PCR_ECCPS (1 << 17)
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/* TAR[16:13]: ALE to RE delay */
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#define FSMC_PCR_TAR (1 << 13)
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/* TCLR[12:9]: CLE to RE delay */
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#define FSMC_PCR_TCLR (1 << 9)
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/* Bits [8..7]: Reserved. */
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/* ECCEN: ECC computation logic enable bit */
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#define FSMC_PCR_ECCEN (1 << 6)
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/* PWID[5:4]: Databus width */
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#define FSMC_PCR_PWID (1 << 4)
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/* PTYP: Memory type */
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#define FSMC_PCR_PTYP (1 << 3)
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/* PBKEN: PC Card/NAND Flash memory bank enable bit */
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#define FSMC_PCR_PBKEN (1 << 2)
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/* PWAITEN: Wait feature enable bit */
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#define FSMC_PCR_PWAITEN (1 << 1)
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/* Bit 0: Reserved. */
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/* --- FSMC_SRx values ----------------------------------------------------- */
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/* Bits [31:7]: Reserved. */
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/* FEMPT: FIFO empty */
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#define FSMC_SR_FEMPT (1 << 6)
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/* IFEN: Interrupt falling edge detection enable bit */
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#define FSMC_SR_IFEN (1 << 5)
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/* ILEN: Interrupt high-level detection enable bit */
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#define FSMC_SR_ILEN (1 << 4)
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/* IREN: Interrupt rising edge detection enable bit */
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#define FSMC_SR_IREN (1 << 3)
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/* IFS: Interrupt falling edge status */
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#define FSMC_SR_IFS (1 << 2)
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/* ILS: Interrupt high-level status */
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#define FSMC_SR_ILS (1 << 1)
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/* IRS: Interrupt rising edge status */
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#define FSMC_SR_IRS (1 << 0)
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/* --- FSMC_PMEMx values --------------------------------------------------- */
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/* MEMHIZx[31:24]: Common memory x databus HiZ time */
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#define FSMC_PMEM_MEMHIZX (1 << 24)
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/* MEMHOLDx[23:16]: Common memory x hold time */
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#define FSMC_PMEM_MEMHOLDX (1 << 16)
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/* MEMWAITx[15:8]: Common memory x wait time */
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#define FSMC_PMEM_MEMWAITX (1 << 8)
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/* MEMSETx[7:0]: Common memory x setup time */
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#define FSMC_PMEM_MEMSETX (1 << 0)
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/* --- FSMC_PATTx values --------------------------------------------------- */
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/* ATTHIZx[31:24]: Attribute memory x databus HiZ time */
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#define FSMC_PATT_ATTHIZX (1 << 24)
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/* ATTHOLDx[23:16]: Attribute memory x hold time */
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#define FSMC_PATT_ATTHOLDX (1 << 16)
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/* ATTWAITx[15:8]: Attribute memory x wait time */
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#define FSMC_PATT_ATTWAITX (1 << 8)
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/* ATTSETx[7:0]: Attribute memory x setup time */
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#define FSMC_PATT_ATTSETX (1 << 0)
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/* --- FSMC_PIO4 values ---------------------------------------------------- */
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/* IOHIZx[31:24]: I/O x databus HiZ time */
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#define FSMC_PIO4_IOHIZX (1 << 24)
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/* IOHOLDx[23:16]: I/O x hold time */
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#define FSMC_PIO4_IOHOLDX (1 << 16)
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/* IOWAITx[15:8]: I/O x wait time */
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#define FSMC_PIO4_IOWAITX (1 << 8)
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/* IOSETx[7:0]: I/O x setup time */
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#define FSMC_PIO4_IOSETX (1 << 0)
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/* --- FSMC_ECCRx values --------------------------------------------------- */
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/* ECCx[31:0]: ECC result */
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#define FSMC_ECCR_ECCX (1 << 0)
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#endif
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