Code for DAC module STM32Fxxx series
Add prototypes to dac.h and small change to simplify alignment enum
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*.swp
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*.swp
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\#*
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\#*
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.\#*
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.\#*
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*~
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*.map
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*.log
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doxygen/
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/** @file
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@ingroup STM32F
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@brief <b>libopencm3 STM32F1xx Digital to Analog Converter</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies
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@date 30 June 2012
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LGPL License Terms @ref lgpl_license
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*/
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/** @defgroup STM32F1xx_dac_defines
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@brief Defined Constants and Types for the STM32F1xx Digital to Analog Converter
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@ingroup STM32F1xx_defines
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LGPL License Terms @ref lgpl_license
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*/
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/*
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/*
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* This file is part of the libopencm3 project.
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* This file is part of the libopencm3 project.
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*
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*
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@ -69,7 +93,7 @@
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/* --- DAC_CR values ------------------------------------------------------- */
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/* --- DAC_CR values ------------------------------------------------------- */
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/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
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/* DMAUDRIE2: DAC channel2 DMA underrun interrupt enable */
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/* doesn't exist in most members of the stm32f1 family */
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/* doesn't exist in most members of the STM32F1 family */
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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#define DAC_CR_DMAUDRIE2 (1 << 29)
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/* DMAEN2: DAC channel2 DMA enable */
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/* DMAEN2: DAC channel2 DMA enable */
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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*/
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*/
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#define DAC_CR_MAMP2_SHIFT 24
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#define DAC_CR_MAMP2_SHIFT 24
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/** @defgroup dac_mamp2 DAC Channel 2 LFSR Mask and Triangle Wave Amplitude values
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@ingroup STM32F1xx_dac_defines
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Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
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@{*/
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#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_1 (0x0 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_2 (0x1 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_3 (0x2 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_10 (0x9 << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_11 (0xA << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
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#define DAC_CR_MAMP2_12 (0xB << DAC_CR_MAMP2_SHIFT)
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/*@}*/
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/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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/* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
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/* Legend:
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/* Legend:
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@ -102,9 +132,18 @@
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* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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* Note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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*/
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*/
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_SHIFT 22
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#define DAC_CR_WAVE2_DIS (0x0 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_DIS (0x3 << DAC_CR_WAVE2_SHIFT)
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/** @defgroup dac_wave2_en DAC Channel 2 Waveform Generation Enable
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@ingroup STM32F1xx_dac_defines
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@li NOISE: Noise wave generation enabled
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@li TRI: Triangle wave generation enabled
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@note: only used if bit TEN2 is set (DAC channel2 trigger enabled)
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@{*/
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#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_NOISE (0x1 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
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#define DAC_CR_WAVE2_TRI (0x2 << DAC_CR_WAVE2_SHIFT)
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/*@}*/
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/* TSEL2[2:0]: DAC channel2 trigger selection */
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/* TSEL2[2:0]: DAC channel2 trigger selection */
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/* Legend:
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/* Legend:
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@ -125,6 +164,25 @@
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* Note: this is *not* valid for the STM32L1 family
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* Note: this is *not* valid for the STM32L1 family
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*/
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*/
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#define DAC_CR_TSEL2_SHIFT 19
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#define DAC_CR_TSEL2_SHIFT 19
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/** @defgroup dac_trig2_sel DAC Channel 2 Trigger Source Selection
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@ingroup STM32F1xx_dac_defines
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@li T6: Timer 6 TRGO event
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@li T3: Timer 3 TRGO event
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@li T8: Timer 8 TRGO event
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@li T7: Timer 7 TRGO event
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@li T5: Timer 5 TRGO event
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@li T15: Timer 15 TRGO event
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@li T2: Timer 2 TRGO event
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@li T4: Timer 4 TRGO event
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@li E9: External line9
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@li SW: Software trigger
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@note: Refer to the timer documentation for details of the TRGO event.
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@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
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@note: this is <b>not</b> valid for the STM32L1 family.
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@note: only used if bit TEN2 is set (DAC channel 2 trigger enabled)
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@{*/
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#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T6 (0x0 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T3 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T8 (0x1 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_T4 (0x5 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_E9 (0x6 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
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#define DAC_CR_TSEL2_SW (0x7 << DAC_CR_TSEL2_SHIFT)
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/*@}*/
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/* TEN2: DAC channel2 trigger enable */
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/* TEN2: DAC channel2 trigger enable */
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#define DAC_CR_TEN2 (1 << 18)
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#define DAC_CR_TEN2 (1 << 18)
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#define DAC_CR_EN2 (1 << 16)
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#define DAC_CR_EN2 (1 << 16)
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/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
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/* DMAUDRIE1: DAC channel1 DMA underrun interrupt enable */
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/* doesn't exist in most members of the stm32f1 family */
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/* doesn't exist in most members of the STM32F1 family */
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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#define DAC_CR_DMAUDRIE1 (1 << 13)
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/* DMAEN1: DAC channel1 DMA enable */
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/* DMAEN1: DAC channel1 DMA enable */
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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* Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**n)-1
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*/
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*/
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#define DAC_CR_MAMP1_SHIFT 8
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#define DAC_CR_MAMP1_SHIFT 8
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/** @defgroup dac_mamp1 DAC Channel 1 LFSR Mask and Triangle Wave Amplitude values
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@ingroup STM32F1xx_dac_defines
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Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
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@{*/
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#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_1 (0x0 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_2 (0x1 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_3 (0x2 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_10 (0x9 << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_11 (0xA << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
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#define DAC_CR_MAMP1_12 (0xB << DAC_CR_MAMP1_SHIFT)
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/*@}*/
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/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
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/* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
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/* Legend:
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/* Legend:
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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* Note: only used if bit TEN1 = 1 (DAC channel1 trigger enabled)
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*/
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*/
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_SHIFT 6
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#define DAC_CR_WAVE1_DIS (0x0 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_DIS (0x3 << DAC_CR_WAVE1_SHIFT)
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/** @defgroup dac_wave1_en DAC Channel 1 Waveform Generation Enable
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@ingroup STM32F1xx_dac_defines
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@li DIS: wave generation disabled
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@li NOISE: Noise wave generation enabled
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@li TRI: Triangle wave generation enabled
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@note: only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
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@{*/
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#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_NOISE (0x1 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
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#define DAC_CR_WAVE1_TRI (0x2 << DAC_CR_WAVE1_SHIFT)
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/*@}*/
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/* TSEL1[2:0]: DAC channel1 trigger selection */
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/* TSEL1[2:0]: DAC channel1 trigger selection */
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/* Legend:
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/* Legend:
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* Note: this is *not* valid for the STM32L1 family
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* Note: this is *not* valid for the STM32L1 family
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*/
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*/
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#define DAC_CR_TSEL1_SHIFT 3
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#define DAC_CR_TSEL1_SHIFT 3
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/** @defgroup dac_trig1_sel DAC Channel 1 Trigger Source Selection
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@ingroup STM32F1xx_dac_defines
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@li T6: Timer 6 TRGO event
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@li T3: Timer 3 TRGO event
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@li T8: Timer 8 TRGO event
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@li T7: Timer 7 TRGO event
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@li T5: Timer 5 TRGO event
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@li T15: Timer 15 TRGO event
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@li T2: Timer 2 TRGO event
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@li T4: Timer 4 TRGO event
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@li E9: External line 9
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@li SW: Software trigger
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@note: Refer to the timer documentation for details of the TRGO event.
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@note: T3 replaced by T8 and T5 replaced by T15 in some devices.
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@note: this is <b>not</b> valid for the STM32L1 family.
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@note: only used if bit TEN2 is set (DAC channel 1 trigger enabled).
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@{*/
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#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T6 (0x0 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T3 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T8 (0x1 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_T4 (0x5 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_E9 (0x6 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
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#define DAC_CR_TSEL1_SW (0x7 << DAC_CR_TSEL1_SHIFT)
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/*@}*/
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/* TEN1: DAC channel1 trigger enable */
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/* TEN1: DAC channel1 trigger enable */
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#define DAC_CR_TEN1 (1 << 2)
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#define DAC_CR_TEN1 (1 << 2)
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#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
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#define DAC_DOR2_DACC2DOR_LSB (1 << 0)
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#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
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#define DAC_DOR2_DACC2DOR_MSK (0x0FFF << 0)
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/** DAC channel identifier */
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typedef enum {
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CHANNEL_1, CHANNEL_2, CHANNEL_D
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} data_channel;
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/** DAC data size (8/12 bits), alignment (right/left) */
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typedef enum {
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RIGHT8, RIGHT12, LEFT12
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} data_align;
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/* --- Function prototypes ------------------------------------------------- */
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/* --- Function prototypes ------------------------------------------------- */
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void dac_enable(data_channel dac_channel);
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/* TODO */
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void dac_disable(data_channel dac_channel);
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void dac_buffer_enable(data_channel dac_channel);
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void dac_buffer_disable(data_channel dac_channel);
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void dac_dma_enable(data_channel dac_channel);
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void dac_dma_disable(data_channel dac_channel);
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void dac_trigger_enable(data_channel dac_channel);
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void dac_trigger_disable(data_channel dac_channel);
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void dac_set_trigger_source(u32 dac_trig_src);
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void dac_set_waveform_generation(u32 dac_wave_ens);
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void dac_disable_waveform_generation(data_channel dac_channel);
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void dac_set_waveform_characteristics(u32 dac_mamp);
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void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel);
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void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format);
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void dac_software_trigger(data_channel dac_channel);
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#endif
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#endif
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/** @file
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@ingroup STM32F
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@brief <b>libopencm3 STM32Fxx Digital to Analog Converter</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2012 Ken Sarkies
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@date 30 June 2012
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This library supports the Digital to Analog Conversion System in the
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STM32F series of ARM Cortex Microcontrollers by ST Microelectronics.
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The DAC is present only in a limited set of devices, notably some
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of the connection line, high density and XL devices.
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Two DAC channels are available, however unlike the ADC channels these
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are separate DAC devices controlled by the same register block.
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The DAC is on APB1. Its clock must be enabled in RCC and the GPIO
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ports set to alternate function output before it can be used.
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The digital output driver is disabled so the output driver mode
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(push-pull/open drain) is arbitrary.
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The DAC has a holding (buffer) register and an output register from
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which the analog output is derived. The holding register must be
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loaded first. If triggering is enabled the output register is loaded
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from the holding register after a trigger occurs. If triggering is
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not enabled the holding register contents are transferred directly
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to the output register.
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@note To avoid nonlinearities, do not allow outputs to range close
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to zero or V_analog.
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@section dac_api_dual Dual Channel Conversion
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There are dual modes in which both DACs are used to output data
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simultaneously or independently on both channels. The data must be
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presented according to the formats described in the datasheets. A
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convenience function @ref dac_load_data_buffer_dual is provided
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for software controlled use.
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A variety of modes are available depending on whether independent
|
||||||
|
or simultaneous output is desired, and whether waveforms are to be
|
||||||
|
superimposed. Refer to the datasheets.
|
||||||
|
|
||||||
|
If DMA is used, only enable it for one of the channels. The DMA
|
||||||
|
requests will then serve data in dual format to the data register
|
||||||
|
dedicated to dual mode. The data will then be split and loaded to the
|
||||||
|
appropriate DAC following the next trigger. There are three registers
|
||||||
|
available, one for each of the formats: 12 bit right-aligned, 12 bit
|
||||||
|
left-aligned and 8 bit right-aligned. The desired format is determined
|
||||||
|
by specifying the appropriate register to the DMA controller.
|
||||||
|
|
||||||
|
@section dac_api_basic_ex Basic DAC handling API.
|
||||||
|
|
||||||
|
Set the DAC's GPIO port to any alternate function output mode. Enable the
|
||||||
|
DAC clock. Enable the DAC, set a trigger source and load the buffer
|
||||||
|
with the first value. After the DAC is triggered, load the buffer with
|
||||||
|
the next value. This example uses software triggering and added noise.
|
||||||
|
The trigger and further buffer load calls are made when data is to be
|
||||||
|
sent out.
|
||||||
|
|
||||||
|
@code
|
||||||
|
gpio_set_mode(GPIOA, GPIO_MODE_OUTPUT_50_MHZ,
|
||||||
|
GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO4);
|
||||||
|
rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_DACEN);
|
||||||
|
dac_disable(CHANNEL_1);
|
||||||
|
dac_set_waveform_characteristics(DAC_CR_MAMP1_8);
|
||||||
|
dac_set_waveform_generation(DAC_CR_WAVE1_NOISE);
|
||||||
|
dac_enable(CHANNEL_1);
|
||||||
|
dac_set_trigger_source(DAC_CR_TSEL1_SW);
|
||||||
|
dac_load_data_buffer_single(0, RIGHT12, CHANNEL_1);
|
||||||
|
....
|
||||||
|
dac_software_trigger(CHANNEL_1);
|
||||||
|
dac_load_data_buffer_single(value, RIGHT12, CHANNEL_1);
|
||||||
|
@endcode
|
||||||
|
|
||||||
|
@section dac_api_dma_ex Simultaneous Dual DAC with DMA.
|
||||||
|
|
||||||
|
This example in part sets up the DAC channel 1 DMA (DMA2 channel 3) to read
|
||||||
|
16 bit data from memory into the right-aligned 8 bit dual register DAC_DHR8RD.
|
||||||
|
Both DAC channels are enabled, and both triggers are set to the same timer
|
||||||
|
2 input as required for simultaneous operation. DMA is enabled for DAC channel
|
||||||
|
1 only to ensure that only one DMA request is generated.
|
||||||
|
|
||||||
|
@code
|
||||||
|
dma_set_memory_size(DMA2,DMA_CHANNEL3,DMA_CCR_MSIZE_16BIT);
|
||||||
|
dma_set_peripheral_size(DMA2,DMA_CHANNEL3,DMA_CCR_PSIZE_16BIT);
|
||||||
|
dma_set_read_from_memory(DMA2,DMA_CHANNEL3);
|
||||||
|
dma_set_peripheral_address(DMA2,DMA_CHANNEL3,(u32) &DAC_DHR8RD);
|
||||||
|
dma_enable_channel(DMA2,DMA_CHANNEL3);
|
||||||
|
...
|
||||||
|
dac_trigger_enable(CHANNEL_D);
|
||||||
|
dac_set_trigger_source(DAC_CR_TSEL1_T2 | DAC_CR_TSEL2_T2);
|
||||||
|
dac_dma_enable(CHANNEL_1);
|
||||||
|
dac_enable(CHANNEL_D);
|
||||||
|
@endcode
|
||||||
|
|
||||||
|
LGPL License Terms @ref lgpl_license
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This file is part of the libopencm3 project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2012 Ken Sarkies
|
||||||
|
*
|
||||||
|
* This library is free software: you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU Lesser General Public License as published by
|
||||||
|
* the Free Software Foundation, either version 3 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This library is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU Lesser General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU Lesser General Public License
|
||||||
|
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <libopencm3/stm32/dac.h>
|
||||||
|
|
||||||
|
#define MASK8 0xFF
|
||||||
|
#define MASK12 0xFFF
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Enable.
|
||||||
|
|
||||||
|
Enable a digital to analog converter channel. After setting this enable, the DAC
|
||||||
|
requires a t<sub>wakeup</sub> time typically around 10 microseconds before it
|
||||||
|
actually wakes up.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_enable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR |= DAC_CR_EN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR |= DAC_CR_EN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR |= (DAC_CR_EN1 | DAC_CR_EN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Disable.
|
||||||
|
|
||||||
|
Disable a digital to analog converter channel.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_disable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR &= ~DAC_CR_EN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR &= ~DAC_CR_EN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR &= ~(DAC_CR_EN1 | DAC_CR_EN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Output Buffer Enable.
|
||||||
|
|
||||||
|
Enable a digital to analog converter channel output drive buffer. This is an optional
|
||||||
|
amplifying buffer that provides additional drive for the output signal. The
|
||||||
|
buffer is enabled by default after a reset and needs to be explicitly disabled
|
||||||
|
if required.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_buffer_enable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR |= DAC_CR_BOFF1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR |= DAC_CR_BOFF2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR |= (DAC_CR_BOFF1 | DAC_CR_BOFF2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Output Buffer Disable.
|
||||||
|
|
||||||
|
Disable a digital to analog converter channel output drive buffer. Disabling this will
|
||||||
|
reduce power consumption slightly and will increase the output impedance of the DAC.
|
||||||
|
The buffers are enabled by default after a reset.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_buffer_disable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR &= ~DAC_CR_BOFF1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR &= ~DAC_CR_BOFF2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR &= ~(DAC_CR_BOFF1 | DAC_CR_BOFF2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel DMA Enable.
|
||||||
|
|
||||||
|
Enable a digital to analog converter channel DMA mode (connected to DMA2 channel
|
||||||
|
3 for DAC channel 1 and DMA2 channel 4 for DAC channel 2). A DMA request is
|
||||||
|
generated following an external trigger.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_dma_enable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR |= DAC_CR_DMAEN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR |= DAC_CR_DMAEN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR |= (DAC_CR_DMAEN1 | DAC_CR_DMAEN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel DMA Disable.
|
||||||
|
|
||||||
|
Disable a digital to analog converter channel DMA mode.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_dma_disable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR &= ~DAC_CR_DMAEN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR &= ~DAC_CR_DMAEN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR &= ~(DAC_CR_DMAEN1 | DAC_CR_DMAEN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Trigger Enable.
|
||||||
|
|
||||||
|
Enable a digital to analog converter channel external trigger mode. This allows an
|
||||||
|
external trigger to initiate register transfers from the buffer register to the DAC
|
||||||
|
output register, followed by a DMA transfer to the buffer register if DMA is enabled.
|
||||||
|
The trigger source must also be selected.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_trigger_enable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR |= DAC_CR_TEN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR |= DAC_CR_TEN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR |= (DAC_CR_TEN1 | DAC_CR_TEN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief DAC Channel Trigger Disable.
|
||||||
|
|
||||||
|
Disable a digital to analog converter channel external trigger.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_trigger_disable(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR &= ~DAC_CR_TEN1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR &= ~DAC_CR_TEN2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR &= ~(DAC_CR_TEN1 | DAC_CR_TEN2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Set DAC Channel Trigger Source.
|
||||||
|
|
||||||
|
Sets the digital to analog converter trigger source, which can be taken from various
|
||||||
|
timers, an external trigger or a software trigger.
|
||||||
|
|
||||||
|
@param[in] u32 dac_trig_src. Taken from @ref dac_trig2_sel or @ref dac_trig1_sel or
|
||||||
|
a logical OR of one of each of these to set both channels simultaneously.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_set_trigger_source(u32 dac_trig_src)
|
||||||
|
{
|
||||||
|
DAC_CR |= dac_trig_src;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Enable and Set DAC Channel Waveform Generation.
|
||||||
|
|
||||||
|
Enable the digital to analog converter waveform generation as either pseudo-random
|
||||||
|
noise or triangular wave. These signals are superimposed on existing output values
|
||||||
|
in the DAC output registers.
|
||||||
|
|
||||||
|
@note The DAC trigger must be enabled for this to work.
|
||||||
|
|
||||||
|
@param[in] u32 dac_trig_src. Taken from @ref dac_wave1_en or @ref dac_wave2_en or
|
||||||
|
a logical OR of one of each of these to set both channels simultaneously.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_set_waveform_generation(u32 dac_wave_ens)
|
||||||
|
{
|
||||||
|
DAC_CR |= dac_wave_ens;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Disable DAC Channel Waveform Generation.
|
||||||
|
|
||||||
|
Disable a digital to analog converter channel superimposed waveform generation.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_disable_waveform_generation(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_CR &= ~DAC_CR_WAVE1_DIS;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_CR &= ~DAC_CR_WAVE2_DIS;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_CR &= ~(DAC_CR_WAVE1_DIS | DAC_CR_WAVE2_DIS);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Set DAC Channel LFSR Mask or Triangle Wave Amplitude.
|
||||||
|
|
||||||
|
Sets the digital to analog converter superimposed waveform generation characteristics.
|
||||||
|
@li If the noise generation mode is set, this sets the length of the PRBS sequence and
|
||||||
|
hence the amplitude of the output noise signal. Default setting is length 1.
|
||||||
|
@li If the triangle wave generation mode is set, this sets the amplitude of the
|
||||||
|
output signal as 2^(n)-1 where n is the parameter value. Default setting is 1.
|
||||||
|
|
||||||
|
@note High amplitude levels of these waveforms can overload the DAC and distort the
|
||||||
|
signal output.
|
||||||
|
@note This must be called before enabling the DAC as the settings will then become read-only.
|
||||||
|
@note The DAC trigger must be enabled for this to work.
|
||||||
|
|
||||||
|
@param[in] u32 dac_mamp. Taken from @ref dac_mamp2 or @ref dac_mamp1 or a logical OR
|
||||||
|
of one of each of these to set both channels simultaneously.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_set_waveform_characteristics(u32 dac_mamp)
|
||||||
|
{
|
||||||
|
DAC_CR |= dac_mamp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Load DAC Data Register.
|
||||||
|
|
||||||
|
Loads the appropriate digital to analog converter data register with 12 or 8 bit
|
||||||
|
data to be converted on a channel. The data can be aligned as follows:
|
||||||
|
@li right-aligned 8 bit data in bits 0-7
|
||||||
|
@li right-aligned 12 bit data in bits 0-11
|
||||||
|
@li left aligned 12 bit data in bits 4-15
|
||||||
|
|
||||||
|
This function can also be used to load the dual channel registers if the data is
|
||||||
|
formatted according to the datasheets:
|
||||||
|
@li right-aligned 8 bit data in bits 0-7 for channel 1 and 8-15 for channel 2
|
||||||
|
@li right-aligned 12 bit data in bits 0-11 for channel 1 and 16-27 for channel 2
|
||||||
|
@li left aligned 12 bit data in bits 4-15 for channel 1 and 20-31 for channel 2
|
||||||
|
|
||||||
|
@param[in] u32 dac_data with appropriate alignment.
|
||||||
|
@param[in] enum ::data_align, dac_data_format. Alignment and size.
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_load_data_buffer_single(u32 dac_data, data_align dac_data_format, data_channel dac_channel)
|
||||||
|
{
|
||||||
|
if (dac_channel == CHANNEL_1)
|
||||||
|
{
|
||||||
|
switch (dac_data_format) {
|
||||||
|
case RIGHT8:
|
||||||
|
DAC_DHR8R1 = dac_data;
|
||||||
|
break;
|
||||||
|
case RIGHT12:
|
||||||
|
DAC_DHR12R1 = dac_data;
|
||||||
|
break;
|
||||||
|
case LEFT12:
|
||||||
|
DAC_DHR12L1 = dac_data;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if (dac_channel == CHANNEL_2)
|
||||||
|
{
|
||||||
|
switch (dac_data_format) {
|
||||||
|
case RIGHT8:
|
||||||
|
DAC_DHR8R2 = dac_data;
|
||||||
|
break;
|
||||||
|
case RIGHT12:
|
||||||
|
DAC_DHR12R2 = dac_data;
|
||||||
|
break;
|
||||||
|
case LEFT12:
|
||||||
|
DAC_DHR12L2 = dac_data;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
switch (dac_data_format) {
|
||||||
|
case RIGHT8:
|
||||||
|
DAC_DHR8RD = dac_data;
|
||||||
|
break;
|
||||||
|
case RIGHT12:
|
||||||
|
DAC_DHR12RD = dac_data;
|
||||||
|
break;
|
||||||
|
case LEFT12:
|
||||||
|
DAC_DHR12LD = dac_data;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Load DAC Dual Data Register.
|
||||||
|
|
||||||
|
Loads the appropriate digital to analog converter dual data register with 12 or
|
||||||
|
8 bit data to be converted for both channels. This allows high bandwidth
|
||||||
|
simultaneous or independent analog output. The data in both channels are aligned
|
||||||
|
identically.
|
||||||
|
|
||||||
|
@param[in] u32 dac_data for channel 1 with appropriate alignment.
|
||||||
|
@param[in] u32 dac_data for channel 2 with appropriate alignment.
|
||||||
|
@param[in] enum ::data_align, dac_data_format. Right or left aligned, and 8 or 12 bit.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data_format)
|
||||||
|
{
|
||||||
|
switch (dac_data_format) {
|
||||||
|
case RIGHT8:
|
||||||
|
DAC_DHR8RD = ((dac_data1 & MASK8) | ((dac_data2 & MASK8) << 8));
|
||||||
|
break;
|
||||||
|
case RIGHT12:
|
||||||
|
DAC_DHR12RD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 12));
|
||||||
|
break;
|
||||||
|
case LEFT12:
|
||||||
|
DAC_DHR12LD = ((dac_data1 & MASK12) | ((dac_data2 & MASK12) << 16));
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------------------------*/
|
||||||
|
/** @brief Trigger the DAC by a Software Trigger.
|
||||||
|
|
||||||
|
If the trigger source is set to be a software trigger, cause a trigger to occur.
|
||||||
|
The trigger is cleared by hardware after conversion.
|
||||||
|
|
||||||
|
@param[in] enum ::data_channel, dac_channel.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void dac_software_trigger(data_channel dac_channel)
|
||||||
|
{
|
||||||
|
switch (dac_channel) {
|
||||||
|
case CHANNEL_1:
|
||||||
|
DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG1;
|
||||||
|
break;
|
||||||
|
case CHANNEL_2:
|
||||||
|
DAC_SWTRIGR |= DAC_SWTRIGR_SWTRIG2;
|
||||||
|
break;
|
||||||
|
case CHANNEL_D:
|
||||||
|
DAC_SWTRIGR |= (DAC_SWTRIGR_SWTRIG1 | DAC_SWTRIGR_SWTRIG2);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
Loading…
Reference in New Issue