2010-10-17 22:36:39 +00:00
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/*
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2010-12-30 12:19:25 +00:00
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* This file is part of the libopencm3 project.
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2010-10-17 22:36:39 +00:00
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*
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* Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Basic TIMER handling API.
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*
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* Examples:
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* timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2,
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* TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
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*/
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2010-12-31 17:18:39 +00:00
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#include <libopencm3/stm32/timer.h>
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2011-09-15 08:18:49 +00:00
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#include <libopencm3/stm32/f1/rcc.h>
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2011-02-01 00:30:12 +00:00
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void timer_reset(u32 timer_peripheral)
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{
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2011-02-03 01:17:15 +00:00
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switch (timer_peripheral) {
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2011-02-01 00:30:12 +00:00
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case TIM1:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM1RST);
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break;
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case TIM2:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM2RST);
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break;
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case TIM3:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM3RST);
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break;
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case TIM4:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM4RST);
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break;
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case TIM5:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM5RST);
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break;
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case TIM6:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM6RST);
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break;
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case TIM7:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM7RST);
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break;
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case TIM8:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM8RST);
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break;
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/* These timers are not supported in libopencm3 yet */
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/*
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case TIM9:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM9RST);
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break;
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case TIM10:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM10RST);
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break;
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case TIM11:
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rcc_peripheral_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
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rcc_peripheral_clear_reset(&RCC_APB2RSTR, RCC_APB2RSTR_TIM11RST);
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break;
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case TIM12:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM12RST);
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break;
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case TIM13:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM13RST);
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break;
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case TIM14:
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rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
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rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_TIM14RST);
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break;
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*/
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}
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}
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2010-10-17 22:36:39 +00:00
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2011-01-31 21:28:54 +00:00
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void timer_enable_irq(u32 timer_peripheral, u32 irq)
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{
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TIM_DIER(timer_peripheral) |= irq;
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}
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void timer_disable_irq(u32 timer_peripheral, u32 irq)
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{
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TIM_DIER(timer_peripheral) &= ~irq;
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}
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2011-02-02 06:43:18 +00:00
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bool timer_get_flag(u32 timer_peripheral, u32 flag)
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{
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if (((TIM_SR(timer_peripheral) & flag) != 0) &&
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((TIM_DIER(timer_peripheral) & flag) != 0)) {
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return true;
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}
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return false;
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}
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2011-02-01 00:15:09 +00:00
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void timer_clear_flag(u32 timer_peripheral, u32 flag)
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{
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TIM_SR(timer_peripheral) &= ~flag;
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}
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2011-01-28 01:03:13 +00:00
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void timer_set_mode(u32 timer_peripheral, u8 clock_div,
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u8 alignment, u8 direction)
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2010-10-17 22:36:39 +00:00
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{
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2011-02-03 01:17:15 +00:00
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u32 cr1;
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cr1 = TIM_CR1(timer_peripheral);
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2011-01-28 01:03:13 +00:00
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2011-11-16 18:31:47 +00:00
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cr1 &= ~(TIM_CR1_CKD_CK_INT_MASK | TIM_CR1_CMS_MASK | TIM_CR1_DIR_DOWN);
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2011-01-28 01:03:13 +00:00
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cr1 |= clock_div | alignment | direction;
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TIM_CR1(timer_peripheral) = cr1;
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2010-10-17 22:36:39 +00:00
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}
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void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
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{
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clock_div &= TIM_CR1_CKD_CK_INT_MASK;
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2011-01-28 01:03:13 +00:00
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_CKD_CK_INT_MASK;
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2010-10-17 22:36:39 +00:00
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TIM_CR1(timer_peripheral) |= clock_div;
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}
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void timer_enable_preload(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
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}
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void timer_disable_preload(u32 timer_peripheral)
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{
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2011-01-28 01:03:13 +00:00
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_ARPE;
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2010-10-17 22:36:39 +00:00
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}
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void timer_set_alignment(u32 timer_peripheral, u32 alignment)
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{
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alignment &= TIM_CR1_CMS_MASK;
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
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TIM_CR1(timer_peripheral) |= alignment;
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}
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void timer_direction_up(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
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}
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void timer_direction_down(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
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}
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void timer_one_shot_mode(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
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}
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void timer_continuous_mode(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
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}
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void timer_update_on_any(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
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}
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void timer_update_on_overflow(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
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}
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void timer_enable_update_event(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
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}
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void timer_disable_update_event(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
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}
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void timer_enable_counter(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
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}
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void timer_disable_counter(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
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}
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void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
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{
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TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
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}
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void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
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{
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TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
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}
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void timer_set_ti1_ch123_xor(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
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}
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void timer_set_ti1_ch1(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
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}
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void timer_set_master_mode(u32 timer_peripheral, u32 mode)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
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TIM_CR2(timer_peripheral) |= mode;
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}
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void timer_set_dma_on_compare_event(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
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}
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void timer_set_dma_on_update_event(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
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}
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void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
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}
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void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
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}
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void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
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}
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void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
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}
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2011-01-28 05:30:07 +00:00
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2011-02-01 06:08:37 +00:00
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void timer_set_prescaler(u32 timer_peripheral, u32 value)
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{
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TIM_PSC(timer_peripheral) = value;
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}
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void timer_set_repetition_counter(u32 timer_peripheral, u32 value)
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{
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2011-02-03 01:17:15 +00:00
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if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
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2011-02-01 06:08:37 +00:00
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TIM_RCR(timer_peripheral) = value;
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}
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2011-01-28 05:30:07 +00:00
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void timer_set_period(u32 timer_peripheral, u32 period)
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{
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TIM_ARR(timer_peripheral) = period;
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}
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void timer_enable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
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{
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switch (oc_id) {
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case TIM_OC1:
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1CE;
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break;
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case TIM_OC2:
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2CE;
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break;
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case TIM_OC3:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3CE;
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break;
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case TIM_OC4:
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TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4CE;
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break;
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case TIM_OC1N:
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case TIM_OC2N:
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case TIM_OC3N:
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/* Ignoring as fast enable only applies to the whole channel. */
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break;
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}
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}
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void timer_disable_oc_clear(u32 timer_peripheral, enum tim_oc_id oc_id)
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{
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switch (oc_id) {
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case TIM_OC1:
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TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1CE;
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break;
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case TIM_OC2:
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TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2CE;
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break;
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case TIM_OC3:
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3CE;
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break;
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case TIM_OC4:
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TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4CE;
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break;
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case TIM_OC1N:
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case TIM_OC2N:
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case TIM_OC3N:
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/* Ignoring as fast enable only applies to the whole channel. */
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break;
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}
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}
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void timer_set_oc_fast_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
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{
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switch (oc_id) {
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case TIM_OC1:
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TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1FE;
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break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as fast enable only applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_slow_mode(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4FE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
void timer_set_oc_mode(u32 timer_peripheral, enum tim_oc_id oc_id,
|
|
|
|
enum tim_oc_mode oc_mode)
|
2011-01-28 05:30:07 +00:00
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK;
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT;
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK;
|
2011-01-28 23:11:52 +00:00
|
|
|
switch (oc_mode) {
|
|
|
|
case TIM_OCM_FROZEN:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_ACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_INACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_TOGGLE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_LOW:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_HIGH:
|
2011-11-16 18:31:47 +00:00
|
|
|
TIM_CCMR1(timer_peripheral) |=
|
|
|
|
TIM_CCMR1_OC1M_FORCE_HIGH;
|
2011-01-28 23:11:52 +00:00
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM1:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM2:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2;
|
|
|
|
break;
|
|
|
|
}
|
2011-01-28 05:30:07 +00:00
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC2S_OUT;
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2M_MASK;
|
2011-01-28 23:11:52 +00:00
|
|
|
switch (oc_mode) {
|
|
|
|
case TIM_OCM_FROZEN:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FROZEN;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_ACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_ACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_INACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_INACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_TOGGLE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_TOGGLE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_LOW:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_FORCE_LOW;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_HIGH:
|
2011-11-16 18:31:47 +00:00
|
|
|
TIM_CCMR1(timer_peripheral) |=
|
|
|
|
TIM_CCMR1_OC2M_FORCE_HIGH;
|
2011-01-28 23:11:52 +00:00
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM1:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM1;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM2:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2M_PWM2;
|
|
|
|
break;
|
|
|
|
}
|
2011-01-28 05:30:07 +00:00
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC3S_MASK;
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC3S_OUT;
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3M_MASK;
|
2011-01-28 23:11:52 +00:00
|
|
|
switch (oc_mode) {
|
|
|
|
case TIM_OCM_FROZEN:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FROZEN;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_ACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC3M_ACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_INACTIVE:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_INACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_TOGGLE:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_TOGGLE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_LOW:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_FORCE_LOW;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_HIGH:
|
2011-11-16 18:31:47 +00:00
|
|
|
TIM_CCMR2(timer_peripheral) |=
|
|
|
|
TIM_CCMR2_OC3M_FORCE_HIGH;
|
2011-01-28 23:11:52 +00:00
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM1:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM1;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM2:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3M_PWM2;
|
|
|
|
break;
|
|
|
|
}
|
2011-01-28 05:30:07 +00:00
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR2_CC4S_MASK;
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_CC4S_OUT;
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4M_MASK;
|
2011-01-28 23:11:52 +00:00
|
|
|
switch (oc_mode) {
|
|
|
|
case TIM_OCM_FROZEN:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FROZEN;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_ACTIVE:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR2_OC4M_ACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_INACTIVE:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_INACTIVE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_TOGGLE:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_TOGGLE;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_LOW:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_FORCE_LOW;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_FORCE_HIGH:
|
2011-11-16 18:31:47 +00:00
|
|
|
TIM_CCMR2(timer_peripheral) |=
|
|
|
|
TIM_CCMR2_OC4M_FORCE_HIGH;
|
2011-01-28 23:11:52 +00:00
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM1:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM1;
|
|
|
|
break;
|
|
|
|
case TIM_OCM_PWM2:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4M_PWM2;
|
|
|
|
break;
|
|
|
|
}
|
2011-01-28 05:30:07 +00:00
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_enable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC2PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC3PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCMR2(timer_peripheral) |= TIM_CCMR2_OC4PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_disable_oc_preload(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC2PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC3PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCMR2(timer_peripheral) &= ~TIM_CCMR2_OC4PE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_polarity_high(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1P;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2P;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3P;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4P;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to TIM1 and TIM8 only. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
/* Acting for TIM1 and TIM8 only from here onwards. */
|
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC1:
|
|
|
|
case TIM_OC2:
|
|
|
|
case TIM_OC3:
|
|
|
|
case TIM_OC4:
|
|
|
|
/* Ignoring as this option was already set above. */
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_polarity_low(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC1P;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC2P;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC3P;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC4P;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to TIM1 and TIM8 only. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
/* Acting for TIM1 and TIM8 only from here onwards. */
|
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NP;
|
|
|
|
break;
|
|
|
|
case TIM_OC1:
|
|
|
|
case TIM_OC2:
|
|
|
|
case TIM_OC3:
|
|
|
|
case TIM_OC4:
|
|
|
|
/* Ignoring as this option was already set above. */
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_enable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC1E;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC2E;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC3E;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC4E;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to TIM1 and TIM8 only. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
/* Acting for TIM1 and TIM8 only from here onwards. */
|
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC1NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC2NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CCER(timer_peripheral) |= TIM_CCER_CC3NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1:
|
|
|
|
case TIM_OC2:
|
|
|
|
case TIM_OC3:
|
|
|
|
case TIM_OC4:
|
|
|
|
/* Ignoring as this option was already set above. */
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_disable_oc_output(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1E;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2E;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3E;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC4E;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to TIM1 and TIM8 only. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
/* Acting for TIM1 and TIM8 only from here onwards. */
|
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC1NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC2NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CCER(timer_peripheral) &= ~TIM_CCER_CC3NE;
|
|
|
|
break;
|
|
|
|
case TIM_OC1:
|
|
|
|
case TIM_OC2:
|
|
|
|
case TIM_OC3:
|
|
|
|
case TIM_OC4:
|
|
|
|
/* Ignoring as this option was already set above. */
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_idle_state_set(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
/* Acting for TIM1 and TIM8 only. */
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS1N;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS2N;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS3N;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CR2(timer_peripheral) |= TIM_CR2_OIS4;
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_idle_state_unset(u32 timer_peripheral, enum tim_oc_id oc_id)
|
|
|
|
{
|
|
|
|
/* Acting for TIM1 and TIM8 only. */
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral != TIM1) && (timer_peripheral != TIM8))
|
|
|
|
return;
|
2011-01-28 05:30:07 +00:00
|
|
|
|
2011-02-03 01:17:15 +00:00
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS1N;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2;
|
|
|
|
break;
|
|
|
|
case TIM_OC2N:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS2N;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3;
|
|
|
|
break;
|
|
|
|
case TIM_OC3N:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS3N;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CR2(timer_peripheral) &= ~TIM_CR2_OIS4;
|
|
|
|
break;
|
2011-01-28 05:30:07 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_oc_value(u32 timer_peripheral, enum tim_oc_id oc_id, u32 value)
|
|
|
|
{
|
|
|
|
switch (oc_id) {
|
|
|
|
case TIM_OC1:
|
|
|
|
TIM_CCR1(timer_peripheral) = value;
|
|
|
|
break;
|
|
|
|
case TIM_OC2:
|
|
|
|
TIM_CCR2(timer_peripheral) = value;
|
|
|
|
break;
|
|
|
|
case TIM_OC3:
|
|
|
|
TIM_CCR3(timer_peripheral) = value;
|
|
|
|
break;
|
|
|
|
case TIM_OC4:
|
|
|
|
TIM_CCR4(timer_peripheral) = value;
|
|
|
|
break;
|
|
|
|
case TIM_OC1N:
|
|
|
|
case TIM_OC2N:
|
|
|
|
case TIM_OC3N:
|
|
|
|
/* Ignoring as this option applies to the whole channel. */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2011-01-29 00:04:36 +00:00
|
|
|
|
|
|
|
void timer_enable_break_main_output(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_MOE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_disable_break_main_output(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_MOE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_enable_break_automatic_output(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_AOE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_disable_break_automatic_output(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_AOE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_break_polarity_high(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKP;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_break_polarity_low(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKP;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_enable_break(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_BKE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_disable_break(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_BKE;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_enabled_off_state_in_run_mode(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSR;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_disabled_off_state_in_run_mode(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSR;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_enabled_off_state_in_idle_mode(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= TIM_BDTR_OSSI;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_disabled_off_state_in_idle_mode(u32 timer_peripheral)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) &= ~TIM_BDTR_OSSI;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_break_lock(u32 timer_peripheral, u32 lock)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= lock;
|
|
|
|
}
|
|
|
|
|
|
|
|
void timer_set_deadtime(u32 timer_peripheral, u32 deadtime)
|
|
|
|
{
|
2011-02-03 01:17:15 +00:00
|
|
|
if ((timer_peripheral == TIM1) || (timer_peripheral == TIM8))
|
2011-01-29 00:04:36 +00:00
|
|
|
TIM_BDTR(timer_peripheral) |= deadtime;
|
|
|
|
}
|
2011-01-31 21:28:54 +00:00
|
|
|
|
|
|
|
void timer_generate_event(u32 timer_peripheral, u32 event)
|
|
|
|
{
|
|
|
|
TIM_EGR(timer_peripheral) |= event;
|
|
|
|
}
|
2011-02-02 06:43:18 +00:00
|
|
|
|
|
|
|
u32 timer_get_counter(u32 timer_peripheral)
|
|
|
|
{
|
|
|
|
return TIM_CNT(timer_peripheral);
|
|
|
|
}
|