2010-10-17 22:36:39 +00:00
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/*
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* This file is part of the libopenstm32 project.
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*
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* Copyright (C) 2010 Edward Cheeseman <evbuilder@users.sourceforge.org>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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* Basic TIMER handling API.
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*
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* Examples:
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* timer_set_mode(TIM1, TIM_CR1_CKD_CK_INT_MUL_2,
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* TIM_CR1_CMS_CENTRE_3, TIM_CR1_DIR_UP);
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*/
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2010-12-30 01:23:51 +00:00
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#include <stm32/timer.h>
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2010-10-17 22:36:39 +00:00
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void timer_set_mode(u32 timer_peripheral, u8 clock_div, u8 alignment,
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u8 direction)
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{
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/* Bad, will reset lots of other stuff. */
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// TIM_CR1(timer_peripheral) = clock_div | alignment | direction;
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}
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void timer_set_clock_division(u32 timer_peripheral, u32 clock_div)
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{
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clock_div &= TIM_CR1_CKD_CK_INT_MASK;
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TIM_CR1(timer_peripheral) &= !TIM_CR1_CKD_CK_INT_MASK;
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TIM_CR1(timer_peripheral) |= clock_div;
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}
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void timer_enable_preload(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_ARPE;
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}
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void timer_disable_preload(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= !TIM_CR1_ARPE;
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}
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void timer_set_alignment(u32 timer_peripheral, u32 alignment)
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{
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alignment &= TIM_CR1_CMS_MASK;
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_CMS_MASK;
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TIM_CR1(timer_peripheral) |= alignment;
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}
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void timer_direction_up(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_DIR_DOWN;
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}
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void timer_direction_down(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_DIR_DOWN;
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}
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void timer_one_shot_mode(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_OPM;
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}
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void timer_continuous_mode(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_OPM;
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}
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void timer_update_on_any(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_URS;
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}
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void timer_update_on_overflow(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_URS;
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}
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void timer_enable_update_event(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_UDIS;
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}
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void timer_disable_update_event(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_UDIS;
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}
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void timer_enable_counter(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) |= TIM_CR1_CEN;
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}
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void timer_disable_counter(u32 timer_peripheral)
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{
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TIM_CR1(timer_peripheral) &= ~TIM_CR1_CEN;
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}
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void timer_set_output_idle_state(u32 timer_peripheral, u32 outputs)
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{
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TIM_CR2(timer_peripheral) |= outputs & TIM_CR2_OIS_MASK;
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}
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void timer_reset_output_idle_state(u32 timer_peripheral, u32 outputs)
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{
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TIM_CR2(timer_peripheral) &= ~(outputs & TIM_CR2_OIS_MASK);
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}
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void timer_set_ti1_ch123_xor(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_TI1S;
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}
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void timer_set_ti1_ch1(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_TI1S;
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}
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void timer_set_master_mode(u32 timer_peripheral, u32 mode)
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{
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mode &= mode & TIM_CR2_MASK;
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_MMS_MASK;
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TIM_CR2(timer_peripheral) |= mode;
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}
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void timer_set_dma_on_compare_event(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCDS;
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}
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void timer_set_dma_on_update_event(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCDS;
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}
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void timer_enable_compare_control_update_on_trigger(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCUS;
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}
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void timer_disable_compare_control_update_on_trigger(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCUS;
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}
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void timer_enable_preload_complementry_enable_bits(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) |= TIM_CR2_CCPC;
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}
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void timer_disable_preload_complementry_enable_bits(u32 timer_peripheral)
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{
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TIM_CR2(timer_peripheral) &= ~TIM_CR2_CCPC;
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}
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