![Michael Sprecher](/assets/img/avatar_default.png)
This is a patch to the et131x driver that fixes up almost all coding style issues Signed-off-by: Michael Sprecher <sprecher.m@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
977 lines
26 KiB
C
977 lines
26 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright * 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_phy.c - Routines for configuring and accessing the PHY
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright * 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#include "et131x_version.h"
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#include "et131x_defs.h"
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/if_arp.h>
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#include <linux/ioport.h>
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#include <linux/random.h>
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#include "et1310_phy.h"
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#include "et131x_adapter.h"
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#include "et1310_address_map.h"
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#include "et1310_tx.h"
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#include "et1310_rx.h"
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#include "et131x.h"
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/* Prototypes for functions with local scope */
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static void et131x_xcvr_init(struct et131x_adapter *etdev);
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/**
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* PhyMiRead - Read from the PHY through the MII Interface on the MAC
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* @etdev: pointer to our private adapter structure
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* @xcvrAddr: the address of the transciever
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* @xcvrReg: the register to read
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* @value: pointer to a 16-bit value in which the value will be stored
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*
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* Returns 0 on success, errno on failure (as defined in errno.h)
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*/
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int PhyMiRead(struct et131x_adapter *etdev, u8 xcvrAddr,
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u8 xcvrReg, u16 *value)
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{
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struct _MAC_t __iomem *mac = &etdev->regs->mac;
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int status = 0;
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u32 delay;
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u32 miiAddr;
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u32 miiCmd;
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u32 miiIndicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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miiAddr = readl(&mac->mii_mgmt_addr);
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miiCmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to read from on the correct PHY */
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writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
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/* Kick the read cycle off */
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delay = 0;
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writel(0x1, &mac->mii_mgmt_cmd);
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do {
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udelay(50);
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delay++;
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miiIndicator = readl(&mac->mii_mgmt_indicator);
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} while ((miiIndicator & MGMT_WAIT) && delay < 50);
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/* If we hit the max delay, we could not read the register */
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if (delay == 50) {
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dev_warn(&etdev->pdev->dev,
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"xcvrReg 0x%08x could not be read\n", xcvrReg);
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dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
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miiIndicator);
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status = -EIO;
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}
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/* If we hit here we were able to read the register and we need to
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* return the value to the caller */
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*value = readl(&mac->mii_mgmt_stat) & 0xFFFF;
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/* Stop the read operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(miiAddr, &mac->mii_mgmt_addr);
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writel(miiCmd, &mac->mii_mgmt_cmd);
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return status;
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}
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/**
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* MiWrite - Write to a PHY register through the MII interface of the MAC
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* @etdev: pointer to our private adapter structure
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* @xcvrReg: the register to read
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* @value: 16-bit value to write
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*
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* FIXME: one caller in netdev still
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*
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* Return 0 on success, errno on failure (as defined in errno.h)
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*/
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int MiWrite(struct et131x_adapter *etdev, u8 xcvrReg, u16 value)
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{
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struct _MAC_t __iomem *mac = &etdev->regs->mac;
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int status = 0;
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u8 xcvrAddr = etdev->Stats.xcvr_addr;
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u32 delay;
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u32 miiAddr;
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u32 miiCmd;
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u32 miiIndicator;
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/* Save a local copy of the registers we are dealing with so we can
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* set them back
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*/
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miiAddr = readl(&mac->mii_mgmt_addr);
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miiCmd = readl(&mac->mii_mgmt_cmd);
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/* Stop the current operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* Set up the register we need to write to on the correct PHY */
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writel(MII_ADDR(xcvrAddr, xcvrReg), &mac->mii_mgmt_addr);
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/* Add the value to write to the registers to the mac */
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writel(value, &mac->mii_mgmt_ctrl);
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delay = 0;
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do {
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udelay(50);
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delay++;
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miiIndicator = readl(&mac->mii_mgmt_indicator);
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} while ((miiIndicator & MGMT_BUSY) && delay < 100);
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/* If we hit the max delay, we could not write the register */
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if (delay == 100) {
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u16 TempValue;
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dev_warn(&etdev->pdev->dev,
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"xcvrReg 0x%08x could not be written", xcvrReg);
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dev_warn(&etdev->pdev->dev, "status is 0x%08x\n",
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miiIndicator);
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dev_warn(&etdev->pdev->dev, "command is 0x%08x\n",
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readl(&mac->mii_mgmt_cmd));
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MiRead(etdev, xcvrReg, &TempValue);
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status = -EIO;
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}
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/* Stop the write operation */
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writel(0, &mac->mii_mgmt_cmd);
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/* set the registers we touched back to the state at which we entered
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* this function
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*/
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writel(miiAddr, &mac->mii_mgmt_addr);
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writel(miiCmd, &mac->mii_mgmt_cmd);
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return status;
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}
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/**
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* et131x_xcvr_find - Find the PHY ID
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* @etdev: pointer to our private adapter structure
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*
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* Returns 0 on success, errno on failure (as defined in errno.h)
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*/
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int et131x_xcvr_find(struct et131x_adapter *etdev)
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{
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u8 xcvr_addr;
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MI_IDR1_t idr1;
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MI_IDR2_t idr2;
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u32 xcvr_id;
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/* We need to get xcvr id and address we just get the first one */
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for (xcvr_addr = 0; xcvr_addr < 32; xcvr_addr++) {
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/* Read the ID from the PHY */
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PhyMiRead(etdev, xcvr_addr,
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(u8) offsetof(MI_REGS_t, idr1),
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&idr1.value);
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PhyMiRead(etdev, xcvr_addr,
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(u8) offsetof(MI_REGS_t, idr2),
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&idr2.value);
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xcvr_id = (u32) ((idr1.value << 16) | idr2.value);
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if (idr1.value != 0 && idr1.value != 0xffff) {
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etdev->Stats.xcvr_id = xcvr_id;
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etdev->Stats.xcvr_addr = xcvr_addr;
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return 0;
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}
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}
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return -ENODEV;
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}
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void ET1310_PhyReset(struct et131x_adapter *etdev)
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{
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MiWrite(etdev, PHY_CONTROL, 0x8000);
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}
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/**
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* ET1310_PhyPowerDown - PHY power control
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* @etdev: device to control
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* @down: true for off/false for back on
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*
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* one hundred, ten, one thousand megs
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* How would you like to have your LAN accessed
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* Can't you see that this code processed
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* Phy power, phy power..
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*/
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void ET1310_PhyPowerDown(struct et131x_adapter *etdev, bool down)
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{
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u16 data;
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MiRead(etdev, PHY_CONTROL, &data);
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data &= ~0x0800; /* Power UP */
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if (down) /* Power DOWN */
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data |= 0x0800;
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MiWrite(etdev, PHY_CONTROL, data);
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}
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/**
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* ET130_PhyAutoNEg - autonegotiate control
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* @etdev: device to control
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* @enabe: autoneg on/off
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*
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* Set up the autonegotiation state according to whether we will be
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* negotiating the state or forcing a speed.
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*/
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static void ET1310_PhyAutoNeg(struct et131x_adapter *etdev, bool enable)
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{
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u16 data;
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MiRead(etdev, PHY_CONTROL, &data);
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data &= ~0x1000; /* Autonegotiation OFF */
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if (enable)
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data |= 0x1000; /* Autonegotiation ON */
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MiWrite(etdev, PHY_CONTROL, data);
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}
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/**
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* ET130_PhyDuplexMode - duplex control
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* @etdev: device to control
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* @duplex: duplex on/off
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*
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* Set up the duplex state on the PHY
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*/
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static void ET1310_PhyDuplexMode(struct et131x_adapter *etdev, u16 duplex)
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{
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u16 data;
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MiRead(etdev, PHY_CONTROL, &data);
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data &= ~0x100; /* Set Half Duplex */
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if (duplex == TRUEPHY_DUPLEX_FULL)
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data |= 0x100; /* Set Full Duplex */
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MiWrite(etdev, PHY_CONTROL, data);
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}
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/**
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* ET130_PhySpeedSelect - speed control
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* @etdev: device to control
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* @duplex: duplex on/off
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*
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* Set the speed of our PHY.
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*/
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static void ET1310_PhySpeedSelect(struct et131x_adapter *etdev, u16 speed)
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{
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u16 data;
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static const u16 bits[3] = {0x0000, 0x2000, 0x0040};
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/* Read the PHY control register */
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MiRead(etdev, PHY_CONTROL, &data);
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/* Clear all Speed settings (Bits 6, 13) */
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data &= ~0x2040;
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/* Write back the new speed */
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MiWrite(etdev, PHY_CONTROL, data | bits[speed]);
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}
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/**
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* ET1310_PhyLinkStatus - read link state
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* @etdev: device to read
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* @link_status: reported link state
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* @autoneg: reported autonegotiation state (complete/incomplete/disabled)
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* @linkspeed: returnedlink speed in use
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* @duplex_mode: reported half/full duplex state
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* @mdi_mdix: not yet working
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* @masterslave: report whether we are master or slave
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* @polarity: link polarity
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*
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* I can read your lan like a magazine
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* I see if your up
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* I know your link speed
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* I see all the setting that you'd rather keep
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*/
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static void ET1310_PhyLinkStatus(struct et131x_adapter *etdev,
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u8 *link_status,
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u32 *autoneg,
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u32 *linkspeed,
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u32 *duplex_mode,
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u32 *mdi_mdix,
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u32 *masterslave, u32 *polarity)
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{
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u16 mistatus = 0;
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u16 is1000BaseT = 0;
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u16 vmi_phystatus = 0;
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u16 control = 0;
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MiRead(etdev, PHY_STATUS, &mistatus);
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MiRead(etdev, PHY_1000_STATUS, &is1000BaseT);
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MiRead(etdev, PHY_PHY_STATUS, &vmi_phystatus);
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MiRead(etdev, PHY_CONTROL, &control);
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*link_status = (vmi_phystatus & 0x0040) ? 1 : 0;
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*autoneg = (control & 0x1000) ? ((vmi_phystatus & 0x0020) ?
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TRUEPHY_ANEG_COMPLETE :
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TRUEPHY_ANEG_NOT_COMPLETE) :
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TRUEPHY_ANEG_DISABLED;
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*linkspeed = (vmi_phystatus & 0x0300) >> 8;
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*duplex_mode = (vmi_phystatus & 0x0080) >> 7;
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/* NOTE: Need to complete this */
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*mdi_mdix = 0;
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*masterslave = (is1000BaseT & 0x4000) ?
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TRUEPHY_CFG_MASTER : TRUEPHY_CFG_SLAVE;
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*polarity = (vmi_phystatus & 0x0400) ?
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TRUEPHY_POLARITY_INVERTED : TRUEPHY_POLARITY_NORMAL;
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}
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static void ET1310_PhyAndOrReg(struct et131x_adapter *etdev,
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u16 regnum, u16 andMask, u16 orMask)
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{
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u16 reg;
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MiRead(etdev, regnum, ®);
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reg &= andMask;
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reg |= orMask;
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MiWrite(etdev, regnum, reg);
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}
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/* Still used from _mac for BIT_READ */
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void ET1310_PhyAccessMiBit(struct et131x_adapter *etdev, u16 action,
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u16 regnum, u16 bitnum, u8 *value)
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{
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u16 reg;
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u16 mask = 0x0001 << bitnum;
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/* Read the requested register */
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MiRead(etdev, regnum, ®);
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switch (action) {
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case TRUEPHY_BIT_READ:
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*value = (reg & mask) >> bitnum;
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break;
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case TRUEPHY_BIT_SET:
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MiWrite(etdev, regnum, reg | mask);
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break;
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case TRUEPHY_BIT_CLEAR:
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MiWrite(etdev, regnum, reg & ~mask);
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break;
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default:
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break;
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}
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}
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void ET1310_PhyAdvertise1000BaseT(struct et131x_adapter *etdev,
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u16 duplex)
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{
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u16 data;
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/* Read the PHY 1000 Base-T Control Register */
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MiRead(etdev, PHY_1000_CONTROL, &data);
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/* Clear Bits 8,9 */
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data &= ~0x0300;
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switch (duplex) {
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case TRUEPHY_ADV_DUPLEX_NONE:
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/* Duplex already cleared, do nothing */
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break;
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case TRUEPHY_ADV_DUPLEX_FULL:
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/* Set Bit 9 */
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data |= 0x0200;
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break;
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case TRUEPHY_ADV_DUPLEX_HALF:
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/* Set Bit 8 */
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data |= 0x0100;
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break;
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case TRUEPHY_ADV_DUPLEX_BOTH:
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default:
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data |= 0x0300;
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break;
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}
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/* Write back advertisement */
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MiWrite(etdev, PHY_1000_CONTROL, data);
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}
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static void ET1310_PhyAdvertise100BaseT(struct et131x_adapter *etdev,
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u16 duplex)
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{
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u16 data;
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/* Read the Autonegotiation Register (10/100) */
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MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
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/* Clear bits 7,8 */
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data &= ~0x0180;
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switch (duplex) {
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case TRUEPHY_ADV_DUPLEX_NONE:
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/* Duplex already cleared, do nothing */
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break;
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case TRUEPHY_ADV_DUPLEX_FULL:
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/* Set Bit 8 */
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data |= 0x0100;
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break;
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case TRUEPHY_ADV_DUPLEX_HALF:
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/* Set Bit 7 */
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data |= 0x0080;
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break;
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case TRUEPHY_ADV_DUPLEX_BOTH:
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default:
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/* Set Bits 7,8 */
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|
data |= 0x0180;
|
|
break;
|
|
}
|
|
|
|
/* Write back advertisement */
|
|
MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
|
|
}
|
|
|
|
static void ET1310_PhyAdvertise10BaseT(struct et131x_adapter *etdev,
|
|
u16 duplex)
|
|
{
|
|
u16 data;
|
|
|
|
/* Read the Autonegotiation Register (10/100) */
|
|
MiRead(etdev, PHY_AUTO_ADVERTISEMENT, &data);
|
|
|
|
/* Clear bits 5,6 */
|
|
data &= ~0x0060;
|
|
|
|
switch (duplex) {
|
|
case TRUEPHY_ADV_DUPLEX_NONE:
|
|
/* Duplex already cleared, do nothing */
|
|
break;
|
|
|
|
case TRUEPHY_ADV_DUPLEX_FULL:
|
|
/* Set Bit 6 */
|
|
data |= 0x0040;
|
|
break;
|
|
|
|
case TRUEPHY_ADV_DUPLEX_HALF:
|
|
/* Set Bit 5 */
|
|
data |= 0x0020;
|
|
break;
|
|
|
|
case TRUEPHY_ADV_DUPLEX_BOTH:
|
|
default:
|
|
/* Set Bits 5,6 */
|
|
data |= 0x0060;
|
|
break;
|
|
}
|
|
|
|
/* Write back advertisement */
|
|
MiWrite(etdev, PHY_AUTO_ADVERTISEMENT, data);
|
|
}
|
|
|
|
/**
|
|
* et131x_setphy_normal - Set PHY for normal operation.
|
|
* @etdev: pointer to our private adapter structure
|
|
*
|
|
* Used by Power Management to force the PHY into 10 Base T half-duplex mode,
|
|
* when going to D3 in WOL mode. Also used during initialization to set the
|
|
* PHY for normal operation.
|
|
*/
|
|
void et131x_setphy_normal(struct et131x_adapter *etdev)
|
|
{
|
|
/* Make sure the PHY is powered up */
|
|
ET1310_PhyPowerDown(etdev, 0);
|
|
et131x_xcvr_init(etdev);
|
|
}
|
|
|
|
|
|
/**
|
|
* et131x_xcvr_init - Init the phy if we are setting it into force mode
|
|
* @etdev: pointer to our private adapter structure
|
|
*
|
|
*/
|
|
static void et131x_xcvr_init(struct et131x_adapter *etdev)
|
|
{
|
|
MI_IMR_t imr;
|
|
MI_ISR_t isr;
|
|
MI_LCR2_t lcr2;
|
|
|
|
/* Zero out the adapter structure variable representing BMSR */
|
|
etdev->Bmsr.value = 0;
|
|
|
|
MiRead(etdev, (u8) offsetof(MI_REGS_t, isr), &isr.value);
|
|
MiRead(etdev, (u8) offsetof(MI_REGS_t, imr), &imr.value);
|
|
|
|
/* Set the link status interrupt only. Bad behavior when link status
|
|
* and auto neg are set, we run into a nested interrupt problem
|
|
*/
|
|
imr.bits.int_en = 0x1;
|
|
imr.bits.link_status = 0x1;
|
|
imr.bits.autoneg_status = 0x1;
|
|
|
|
MiWrite(etdev, (u8) offsetof(MI_REGS_t, imr), imr.value);
|
|
|
|
/* Set the LED behavior such that LED 1 indicates speed (off =
|
|
* 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
|
|
* link and activity (on for link, blink off for activity).
|
|
*
|
|
* NOTE: Some customizations have been added here for specific
|
|
* vendors; The LED behavior is now determined by vendor data in the
|
|
* EEPROM. However, the above description is the default.
|
|
*/
|
|
if ((etdev->eepromData[1] & 0x4) == 0) {
|
|
MiRead(etdev, (u8) offsetof(MI_REGS_t, lcr2),
|
|
&lcr2.value);
|
|
if ((etdev->eepromData[1] & 0x8) == 0)
|
|
lcr2.bits.led_tx_rx = 0x3;
|
|
else
|
|
lcr2.bits.led_tx_rx = 0x4;
|
|
lcr2.bits.led_link = 0xa;
|
|
MiWrite(etdev, (u8) offsetof(MI_REGS_t, lcr2),
|
|
lcr2.value);
|
|
}
|
|
|
|
/* Determine if we need to go into a force mode and set it */
|
|
if (etdev->AiForceSpeed == 0 && etdev->AiForceDpx == 0) {
|
|
if (etdev->RegistryFlowControl == TxOnly ||
|
|
etdev->RegistryFlowControl == Both)
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_SET, 4, 11, NULL);
|
|
else
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_CLEAR, 4, 11, NULL);
|
|
|
|
if (etdev->RegistryFlowControl == Both)
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_SET, 4, 10, NULL);
|
|
else
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_CLEAR, 4, 10, NULL);
|
|
|
|
/* Set the phy to autonegotiation */
|
|
ET1310_PhyAutoNeg(etdev, true);
|
|
|
|
/* NOTE - Do we need this? */
|
|
ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_SET, 0, 9, NULL);
|
|
return;
|
|
}
|
|
|
|
ET1310_PhyAutoNeg(etdev, false);
|
|
|
|
/* Set to the correct force mode. */
|
|
if (etdev->AiForceDpx != 1) {
|
|
if (etdev->RegistryFlowControl == TxOnly ||
|
|
etdev->RegistryFlowControl == Both)
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_SET, 4, 11, NULL);
|
|
else
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_CLEAR, 4, 11, NULL);
|
|
|
|
if (etdev->RegistryFlowControl == Both)
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_SET, 4, 10, NULL);
|
|
else
|
|
ET1310_PhyAccessMiBit(etdev,
|
|
TRUEPHY_BIT_CLEAR, 4, 10, NULL);
|
|
} else {
|
|
ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 10, NULL);
|
|
ET1310_PhyAccessMiBit(etdev, TRUEPHY_BIT_CLEAR, 4, 11, NULL);
|
|
}
|
|
ET1310_PhyPowerDown(etdev, 1);
|
|
switch (etdev->AiForceSpeed) {
|
|
case 10:
|
|
/* First we need to turn off all other advertisement */
|
|
ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
if (etdev->AiForceDpx == 1) {
|
|
/* Set our advertise values accordingly */
|
|
ET1310_PhyAdvertise10BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_HALF);
|
|
} else if (etdev->AiForceDpx == 2) {
|
|
/* Set our advertise values accordingly */
|
|
ET1310_PhyAdvertise10BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_FULL);
|
|
} else {
|
|
/* Disable autoneg */
|
|
ET1310_PhyAutoNeg(etdev, false);
|
|
/* Disable rest of the advertisements */
|
|
ET1310_PhyAdvertise10BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_NONE);
|
|
/* Force 10 Mbps */
|
|
ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_10MBPS);
|
|
/* Force Full duplex */
|
|
ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
|
|
}
|
|
break;
|
|
case 100:
|
|
/* first we need to turn off all other advertisement */
|
|
ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
if (etdev->AiForceDpx == 1) {
|
|
/* Set our advertise values accordingly */
|
|
ET1310_PhyAdvertise100BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_HALF);
|
|
/* Set speed */
|
|
ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
|
|
} else if (etdev->AiForceDpx == 2) {
|
|
/* Set our advertise values accordingly */
|
|
ET1310_PhyAdvertise100BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_FULL);
|
|
} else {
|
|
/* Disable autoneg */
|
|
ET1310_PhyAutoNeg(etdev, false);
|
|
/* Disable other advertisement */
|
|
ET1310_PhyAdvertise100BaseT(etdev,
|
|
TRUEPHY_ADV_DUPLEX_NONE);
|
|
/* Force 100 Mbps */
|
|
ET1310_PhySpeedSelect(etdev, TRUEPHY_SPEED_100MBPS);
|
|
/* Force Full duplex */
|
|
ET1310_PhyDuplexMode(etdev, TRUEPHY_DUPLEX_FULL);
|
|
}
|
|
break;
|
|
case 1000:
|
|
/* first we need to turn off all other advertisement */
|
|
ET1310_PhyAdvertise100BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
ET1310_PhyAdvertise10BaseT(etdev, TRUEPHY_ADV_DUPLEX_NONE);
|
|
/* set our advertise values accordingly */
|
|
ET1310_PhyAdvertise1000BaseT(etdev, TRUEPHY_ADV_DUPLEX_FULL);
|
|
break;
|
|
}
|
|
ET1310_PhyPowerDown(etdev, 0);
|
|
}
|
|
|
|
void et131x_Mii_check(struct et131x_adapter *etdev,
|
|
MI_BMSR_t bmsr, MI_BMSR_t bmsr_ints)
|
|
{
|
|
u8 link_status;
|
|
u32 autoneg_status;
|
|
u32 speed;
|
|
u32 duplex;
|
|
u32 mdi_mdix;
|
|
u32 masterslave;
|
|
u32 polarity;
|
|
unsigned long flags;
|
|
|
|
if (bmsr_ints.bits.link_status) {
|
|
if (bmsr.bits.link_status) {
|
|
etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
|
|
|
|
/* Update our state variables and indicate the
|
|
* connected state
|
|
*/
|
|
spin_lock_irqsave(&etdev->Lock, flags);
|
|
|
|
etdev->MediaState = NETIF_STATUS_MEDIA_CONNECT;
|
|
etdev->Flags &= ~fMP_ADAPTER_LINK_DETECTION;
|
|
|
|
spin_unlock_irqrestore(&etdev->Lock, flags);
|
|
|
|
netif_carrier_on(etdev->netdev);
|
|
} else {
|
|
dev_warn(&etdev->pdev->dev,
|
|
"Link down - cable problem ?\n");
|
|
|
|
if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
|
|
/* NOTE - Is there a way to query this without
|
|
* TruePHY?
|
|
* && TRU_QueryCoreType(etdev->hTruePhy, 0) == EMI_TRUEPHY_A13O) {
|
|
*/
|
|
u16 Register18;
|
|
|
|
MiRead(etdev, 0x12, &Register18);
|
|
MiWrite(etdev, 0x12, Register18 | 0x4);
|
|
MiWrite(etdev, 0x10, Register18 | 0x8402);
|
|
MiWrite(etdev, 0x11, Register18 | 511);
|
|
MiWrite(etdev, 0x12, Register18);
|
|
}
|
|
|
|
/* For the first N seconds of life, we are in "link
|
|
* detection" When we are in this state, we should
|
|
* only report "connected". When the LinkDetection
|
|
* Timer expires, we can report disconnected (handled
|
|
* in the LinkDetectionDPC).
|
|
*/
|
|
if (!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
|
|
(etdev->MediaState == NETIF_STATUS_MEDIA_DISCONNECT)) {
|
|
spin_lock_irqsave(&etdev->Lock, flags);
|
|
etdev->MediaState =
|
|
NETIF_STATUS_MEDIA_DISCONNECT;
|
|
spin_unlock_irqrestore(&etdev->Lock,
|
|
flags);
|
|
|
|
netif_carrier_off(etdev->netdev);
|
|
}
|
|
|
|
etdev->linkspeed = 0;
|
|
etdev->duplex_mode = 0;
|
|
|
|
/* Free the packets being actively sent & stopped */
|
|
et131x_free_busy_send_packets(etdev);
|
|
|
|
/* Re-initialize the send structures */
|
|
et131x_init_send(etdev);
|
|
|
|
/* Reset the RFD list and re-start RU */
|
|
et131x_reset_recv(etdev);
|
|
|
|
/*
|
|
* Bring the device back to the state it was during
|
|
* init prior to autonegotiation being complete. This
|
|
* way, when we get the auto-neg complete interrupt,
|
|
* we can complete init by calling ConfigMacREGS2.
|
|
*/
|
|
et131x_soft_reset(etdev);
|
|
|
|
/* Setup ET1310 as per the documentation */
|
|
et131x_adapter_setup(etdev);
|
|
|
|
/* Setup the PHY into coma mode until the cable is
|
|
* plugged back in
|
|
*/
|
|
if (etdev->RegistryPhyComa == 1)
|
|
EnablePhyComa(etdev);
|
|
}
|
|
}
|
|
|
|
if (bmsr_ints.bits.auto_neg_complete ||
|
|
(etdev->AiForceDpx == 3 && bmsr_ints.bits.link_status)) {
|
|
if (bmsr.bits.auto_neg_complete || etdev->AiForceDpx == 3) {
|
|
ET1310_PhyLinkStatus(etdev,
|
|
&link_status, &autoneg_status,
|
|
&speed, &duplex, &mdi_mdix,
|
|
&masterslave, &polarity);
|
|
|
|
etdev->linkspeed = speed;
|
|
etdev->duplex_mode = duplex;
|
|
|
|
etdev->PoMgmt.TransPhyComaModeOnBoot = 20;
|
|
|
|
if (etdev->linkspeed == TRUEPHY_SPEED_10MBPS) {
|
|
/*
|
|
* NOTE - Is there a way to query this without
|
|
* TruePHY?
|
|
* && TRU_QueryCoreType(etdev->hTruePhy, 0)== EMI_TRUEPHY_A13O) {
|
|
*/
|
|
u16 Register18;
|
|
|
|
MiRead(etdev, 0x12, &Register18);
|
|
MiWrite(etdev, 0x12, Register18 | 0x4);
|
|
MiWrite(etdev, 0x10, Register18 | 0x8402);
|
|
MiWrite(etdev, 0x11, Register18 | 511);
|
|
MiWrite(etdev, 0x12, Register18);
|
|
}
|
|
|
|
ConfigFlowControl(etdev);
|
|
|
|
if (etdev->linkspeed == TRUEPHY_SPEED_1000MBPS &&
|
|
etdev->RegistryJumboPacket > 2048)
|
|
ET1310_PhyAndOrReg(etdev, 0x16, 0xcfff,
|
|
0x2000);
|
|
|
|
SetRxDmaTimer(etdev);
|
|
ConfigMACRegs2(etdev);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The routines which follow provide low-level access to the PHY, and are used
|
|
* primarily by the routines above (although there are a few places elsewhere
|
|
* in the driver where this level of access is required).
|
|
*/
|
|
|
|
static const u16 ConfigPhy[25][2] = {
|
|
/* Reg Value Register */
|
|
/* Addr */
|
|
{0x880B, 0x0926}, /* AfeIfCreg4B1000Msbs */
|
|
{0x880C, 0x0926}, /* AfeIfCreg4B100Msbs */
|
|
{0x880D, 0x0926}, /* AfeIfCreg4B10Msbs */
|
|
|
|
{0x880E, 0xB4D3}, /* AfeIfCreg4B1000Lsbs */
|
|
{0x880F, 0xB4D3}, /* AfeIfCreg4B100Lsbs */
|
|
{0x8810, 0xB4D3}, /* AfeIfCreg4B10Lsbs */
|
|
|
|
{0x8805, 0xB03E}, /* AfeIfCreg3B1000Msbs */
|
|
{0x8806, 0xB03E}, /* AfeIfCreg3B100Msbs */
|
|
{0x8807, 0xFF00}, /* AfeIfCreg3B10Msbs */
|
|
|
|
{0x8808, 0xE090}, /* AfeIfCreg3B1000Lsbs */
|
|
{0x8809, 0xE110}, /* AfeIfCreg3B100Lsbs */
|
|
{0x880A, 0x0000}, /* AfeIfCreg3B10Lsbs */
|
|
|
|
{0x300D, 1}, /* DisableNorm */
|
|
|
|
{0x280C, 0x0180}, /* LinkHoldEnd */
|
|
|
|
{0x1C21, 0x0002}, /* AlphaM */
|
|
|
|
{0x3821, 6}, /* FfeLkgTx0 */
|
|
{0x381D, 1}, /* FfeLkg1g4 */
|
|
{0x381E, 1}, /* FfeLkg1g5 */
|
|
{0x381F, 1}, /* FfeLkg1g6 */
|
|
{0x3820, 1}, /* FfeLkg1g7 */
|
|
|
|
{0x8402, 0x01F0}, /* Btinact */
|
|
{0x800E, 20}, /* LftrainTime */
|
|
{0x800F, 24}, /* DvguardTime */
|
|
{0x8010, 46}, /* IdlguardTime */
|
|
|
|
{0, 0}
|
|
|
|
};
|
|
|
|
/* condensed version of the phy initialization routine */
|
|
void ET1310_PhyInit(struct et131x_adapter *etdev)
|
|
{
|
|
u16 data, index;
|
|
|
|
if (etdev == NULL)
|
|
return;
|
|
|
|
/* get the identity (again ?) */
|
|
MiRead(etdev, PHY_ID_1, &data);
|
|
MiRead(etdev, PHY_ID_2, &data);
|
|
|
|
/* what does this do/achieve ? */
|
|
MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
|
|
|
|
/* read modem register 0402, should I do something with the return
|
|
data ? */
|
|
MiWrite(etdev, PHY_INDEX_REG, 0x0402);
|
|
MiRead(etdev, PHY_DATA_REG, &data);
|
|
|
|
/* what does this do/achieve ? */
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
|
|
|
|
/* get the identity (again ?) */
|
|
MiRead(etdev, PHY_ID_1, &data);
|
|
MiRead(etdev, PHY_ID_2, &data);
|
|
|
|
/* what does this achieve ? */
|
|
MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0006);
|
|
|
|
/* read modem register 0402, should I do something with
|
|
the return data? */
|
|
MiWrite(etdev, PHY_INDEX_REG, 0x0402);
|
|
MiRead(etdev, PHY_DATA_REG, &data);
|
|
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
|
|
|
|
/* what does this achieve (should return 0x1040) */
|
|
MiRead(etdev, PHY_CONTROL, &data);
|
|
MiRead(etdev, PHY_MPHY_CONTROL_REG, &data); /* should read 0002 */
|
|
MiWrite(etdev, PHY_CONTROL, 0x1840);
|
|
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0007);
|
|
|
|
/* here the writing of the array starts.... */
|
|
index = 0;
|
|
while (ConfigPhy[index][0] != 0x0000) {
|
|
/* write value */
|
|
MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
|
|
MiWrite(etdev, PHY_DATA_REG, ConfigPhy[index][1]);
|
|
|
|
/* read it back */
|
|
MiWrite(etdev, PHY_INDEX_REG, ConfigPhy[index][0]);
|
|
MiRead(etdev, PHY_DATA_REG, &data);
|
|
|
|
/* do a check on the value read back ? */
|
|
index++;
|
|
}
|
|
/* here the writing of the array ends... */
|
|
|
|
MiRead(etdev, PHY_CONTROL, &data); /* 0x1840 */
|
|
MiRead(etdev, PHY_MPHY_CONTROL_REG, &data);/* should read 0007 */
|
|
MiWrite(etdev, PHY_CONTROL, 0x1040);
|
|
MiWrite(etdev, PHY_MPHY_CONTROL_REG, 0x0002);
|
|
}
|
|
|