![Jean Delvare](/assets/img/avatar_default.png)
The original i2c-algo-bit implementation uses a 33/66 SCL duty cycle when bits are being written on the bus. While the I2C specification doesn't forbid it, this prevents us from driving the I2C bus to its max speed, limiting us to 66 kbps max on standard I2C busses. Implementing a 50/50 duty cycle instead lets us max out the bandwidth up to the theoretical max of 100 kbps on standard I2C busses. This is particularly important when large amounts of data need to be transfered over the bus, as is the case with some TV adapters when the firmware is being uploaded. In fact this change even allows, at least in theory, fast-mode I2C support at 125, 166 and 250 kbps. There's no way to reach the theoretical max of 400 kbps with this implementation. But I don't think we want to put efforts in that direction anyway: software-driven I2C is very CPU-intensive and bad for latency. Other timing changes: * Don't set SDA high explicitly on error, we're going to issue a stop condition before we leave anyway. * If an error occurs when sending the slave address, yield the CPU before retrying, and remove the additional delay after the new start condition. Signed-off-by: Jean Delvare <khali@linux-fr.org>
52 lines
2.1 KiB
C
52 lines
2.1 KiB
C
/* ------------------------------------------------------------------------- */
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/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */
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/* ------------------------------------------------------------------------- */
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/* Copyright (C) 1995-99 Simon G. Vogl
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* ------------------------------------------------------------------------- */
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/* With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
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Frodo Looijaard <frodol@dds.nl> */
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#ifndef _LINUX_I2C_ALGO_BIT_H
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#define _LINUX_I2C_ALGO_BIT_H
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/* --- Defines for bit-adapters --------------------------------------- */
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/*
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* This struct contains the hw-dependent functions of bit-style adapters to
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* manipulate the line states, and to init any hw-specific features. This is
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* only used if you have more than one hw-type of adapter running.
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*/
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struct i2c_algo_bit_data {
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void *data; /* private data for lowlevel routines */
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void (*setsda) (void *data, int state);
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void (*setscl) (void *data, int state);
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int (*getsda) (void *data);
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int (*getscl) (void *data);
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/* local settings */
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int udelay; /* half clock cycle time in us,
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minimum 2 us for fast-mode I2C,
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minimum 5 us for standard-mode I2C and SMBus,
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maximum 50 us for SMBus */
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int timeout; /* in jiffies */
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};
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int i2c_bit_add_bus(struct i2c_adapter *);
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int i2c_bit_add_numbered_bus(struct i2c_adapter *);
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#endif /* _LINUX_I2C_ALGO_BIT_H */
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