3bfb1d20b5
This adds a driver for the Synopsys DesignWare DMA controller (aka DMACA on AVR32 systems.) This DMA controller can be found integrated on the AT32AP7000 chip and is primarily meant for peripheral DMA transfer, but can also be used for memory-to-memory transfers. This patch is based on a driver from David Brownell which was based on an older version of the DMA Engine framework. It also implements the proposed extensions to the DMA Engine API for slave DMA operations. The dmatest client shows no problems, but there may still be room for improvement performance-wise. DMA slave transfer performance is definitely "good enough"; reading 100 MiB from an SD card running at ~20 MHz yields ~7.2 MiB/s average transfer rate. Full documentation for this controller can be found in the Synopsys DW AHB DMAC Databook: http://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf The controller has lots of implementation options, so it's usually a good idea to check the data sheet of the chip it's intergrated on as well. The AT32AP7000 data sheet can be found here: http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Changes since v4: * Use client_count instead of dma_chan_is_in_use() * Add missing include * Unmap buffers unless client told us not to Changes since v3: * Update to latest DMA engine and DMA slave APIs * Embed the hw descriptor into the sw descriptor * Clean up and update MODULE_DESCRIPTION, copyright date, etc. Changes since v2: * Dequeue all pending transfers in terminate_all() * Rename dw_dmac.h -> dw_dmac_regs.h * Define and use controller-specific dma_slave data * Fix up a few outdated comments * Define hardware registers as structs (doesn't generate better code, unfortunately, but it looks nicer.) * Get number of channels from platform_data instead of hardcoding it based on CONFIG_WHATEVER_CPU. * Give slave clients exclusive access to the channel Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>, Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
50 lines
1.3 KiB
C
50 lines
1.3 KiB
C
/*
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* Pin definitions for AT32AP7000.
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*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_AT32AP700X_H__
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#define __ASM_ARCH_AT32AP700X_H__
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#define GPIO_PERIPH_A 0
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#define GPIO_PERIPH_B 1
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/*
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* Pin numbers identifying specific GPIO pins on the chip. They can
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* also be converted to IRQ numbers by passing them through
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* gpio_to_irq().
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*/
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#define GPIO_PIOA_BASE (0)
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#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
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#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
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#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
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#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
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#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
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#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
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#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
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#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
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#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
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/*
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* DMAC peripheral hardware handshaking interfaces, used with dw_dmac
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*/
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#define DMAC_MCI_RX 0
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#define DMAC_MCI_TX 1
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#define DMAC_DAC_TX 2
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#define DMAC_AC97_A_RX 3
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#define DMAC_AC97_A_TX 4
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#define DMAC_AC97_B_RX 5
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#define DMAC_AC97_B_TX 6
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#define DMAC_DMAREQ_0 7
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#define DMAC_DMAREQ_1 8
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#define DMAC_DMAREQ_2 9
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#define DMAC_DMAREQ_3 10
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#endif /* __ASM_ARCH_AT32AP700X_H__ */
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