dmaengine: Driver for the Synopsys DesignWare DMA controller
This adds a driver for the Synopsys DesignWare DMA controller (aka DMACA on AVR32 systems.) This DMA controller can be found integrated on the AT32AP7000 chip and is primarily meant for peripheral DMA transfer, but can also be used for memory-to-memory transfers. This patch is based on a driver from David Brownell which was based on an older version of the DMA Engine framework. It also implements the proposed extensions to the DMA Engine API for slave DMA operations. The dmatest client shows no problems, but there may still be room for improvement performance-wise. DMA slave transfer performance is definitely "good enough"; reading 100 MiB from an SD card running at ~20 MHz yields ~7.2 MiB/s average transfer rate. Full documentation for this controller can be found in the Synopsys DW AHB DMAC Databook: http://www.synopsys.com/designware/docs/iip/DW_ahb_dmac/latest/doc/dw_ahb_dmac_db.pdf The controller has lots of implementation options, so it's usually a good idea to check the data sheet of the chip it's intergrated on as well. The AT32AP7000 data sheet can be found here: http://www.atmel.com/dyn/products/datasheets.asp?family_id=682 Changes since v4: * Use client_count instead of dma_chan_is_in_use() * Add missing include * Unmap buffers unless client told us not to Changes since v3: * Update to latest DMA engine and DMA slave APIs * Embed the hw descriptor into the sw descriptor * Clean up and update MODULE_DESCRIPTION, copyright date, etc. Changes since v2: * Dequeue all pending transfers in terminate_all() * Rename dw_dmac.h -> dw_dmac_regs.h * Define and use controller-specific dma_slave data * Fix up a few outdated comments * Define hardware registers as structs (doesn't generate better code, unfortunately, but it looks nicer.) * Get number of channels from platform_data instead of hardcoding it based on CONFIG_WHATEVER_CPU. * Give slave clients exclusive access to the channel Acked-by: Maciej Sosnowski <maciej.sosnowski@intel.com>, Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Haavard Skinnemoen
Dan Williams
parent
dc0ee6435c
commit
3bfb1d20b5
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@ -7,6 +7,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dw_dmac.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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@ -599,6 +600,17 @@ static void __init genclk_init_parent(struct clk *clk)
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clk->parent = parent;
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}
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static struct dw_dma_platform_data dw_dmac0_data = {
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.nr_channels = 3,
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};
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static struct resource dw_dmac0_resource[] = {
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PBMEM(0xff200000),
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IRQ(2),
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};
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DEFINE_DEV_DATA(dw_dmac, 0);
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DEV_CLK(hclk, dw_dmac0, hsb, 10);
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/* --------------------------------------------------------------------
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* System peripherals
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* -------------------------------------------------------------------- */
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@ -705,17 +717,6 @@ static struct clk pico_clk = {
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.users = 1,
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};
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static struct resource dmaca0_resource[] = {
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{
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.start = 0xff200000,
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.end = 0xff20ffff,
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.flags = IORESOURCE_MEM,
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},
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IRQ(2),
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};
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DEFINE_DEV(dmaca, 0);
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DEV_CLK(hclk, dmaca0, hsb, 10);
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/* --------------------------------------------------------------------
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* HMATRIX
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* -------------------------------------------------------------------- */
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@ -828,7 +829,7 @@ void __init at32_add_system_devices(void)
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platform_device_register(&at32_eic0_device);
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platform_device_register(&smc0_device);
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platform_device_register(&pdc_device);
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platform_device_register(&dmaca0_device);
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platform_device_register(&dw_dmac0_device);
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platform_device_register(&at32_tcb0_device);
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platform_device_register(&at32_tcb1_device);
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@ -1891,7 +1892,7 @@ struct clk *at32_clock_list[] = {
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&smc0_mck,
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&pdc_hclk,
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&pdc_pclk,
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&dmaca0_hclk,
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&dw_dmac0_hclk,
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&pico_clk,
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&pio0_mck,
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&pio1_mck,
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@ -38,6 +38,15 @@ config INTEL_IOP_ADMA
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help
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Enable support for the Intel(R) IOP Series RAID engines.
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config DW_DMAC
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tristate "Synopsys DesignWare AHB DMA support"
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depends on AVR32
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select DMA_ENGINE
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default y if CPU_AT32AP7000
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help
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Support the Synopsys DesignWare AHB DMA controller. This
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can be integrated in chips such as the Atmel AT32ap7000.
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config FSL_DMA
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bool "Freescale MPC85xx/MPC83xx DMA support"
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depends on PPC
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@ -6,3 +6,4 @@ ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
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obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
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obj-$(CONFIG_FSL_DMA) += fsldma.o
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obj-$(CONFIG_MV_XOR) += mv_xor.o
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obj-$(CONFIG_DW_DMAC) += dw_dmac.o
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,225 @@
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/*
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* Driver for the Synopsys DesignWare AHB DMA Controller
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*
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* Copyright (C) 2005-2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/dw_dmac.h>
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#define DW_DMA_MAX_NR_CHANNELS 8
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/*
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* Redefine this macro to handle differences between 32- and 64-bit
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* addressing, big vs. little endian, etc.
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*/
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#define DW_REG(name) u32 name; u32 __pad_##name
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/* Hardware register definitions. */
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struct dw_dma_chan_regs {
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DW_REG(SAR); /* Source Address Register */
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DW_REG(DAR); /* Destination Address Register */
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DW_REG(LLP); /* Linked List Pointer */
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u32 CTL_LO; /* Control Register Low */
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u32 CTL_HI; /* Control Register High */
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DW_REG(SSTAT);
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DW_REG(DSTAT);
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DW_REG(SSTATAR);
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DW_REG(DSTATAR);
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u32 CFG_LO; /* Configuration Register Low */
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u32 CFG_HI; /* Configuration Register High */
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DW_REG(SGR);
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DW_REG(DSR);
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};
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struct dw_dma_irq_regs {
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DW_REG(XFER);
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DW_REG(BLOCK);
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DW_REG(SRC_TRAN);
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DW_REG(DST_TRAN);
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DW_REG(ERROR);
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};
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struct dw_dma_regs {
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/* per-channel registers */
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struct dw_dma_chan_regs CHAN[DW_DMA_MAX_NR_CHANNELS];
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/* irq handling */
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struct dw_dma_irq_regs RAW; /* r */
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struct dw_dma_irq_regs STATUS; /* r (raw & mask) */
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struct dw_dma_irq_regs MASK; /* rw (set = irq enabled) */
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struct dw_dma_irq_regs CLEAR; /* w (ack, affects "raw") */
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DW_REG(STATUS_INT); /* r */
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/* software handshaking */
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DW_REG(REQ_SRC);
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DW_REG(REQ_DST);
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DW_REG(SGL_REQ_SRC);
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DW_REG(SGL_REQ_DST);
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DW_REG(LAST_SRC);
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DW_REG(LAST_DST);
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/* miscellaneous */
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DW_REG(CFG);
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DW_REG(CH_EN);
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DW_REG(ID);
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DW_REG(TEST);
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/* optional encoded params, 0x3c8..0x3 */
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};
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/* Bitfields in CTL_LO */
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#define DWC_CTLL_INT_EN (1 << 0) /* irqs enabled? */
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#define DWC_CTLL_DST_WIDTH(n) ((n)<<1) /* bytes per element */
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#define DWC_CTLL_SRC_WIDTH(n) ((n)<<4)
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#define DWC_CTLL_DST_INC (0<<7) /* DAR update/not */
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#define DWC_CTLL_DST_DEC (1<<7)
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#define DWC_CTLL_DST_FIX (2<<7)
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#define DWC_CTLL_SRC_INC (0<<7) /* SAR update/not */
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#define DWC_CTLL_SRC_DEC (1<<9)
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#define DWC_CTLL_SRC_FIX (2<<9)
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#define DWC_CTLL_DST_MSIZE(n) ((n)<<11) /* burst, #elements */
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#define DWC_CTLL_SRC_MSIZE(n) ((n)<<14)
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#define DWC_CTLL_S_GATH_EN (1 << 17) /* src gather, !FIX */
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#define DWC_CTLL_D_SCAT_EN (1 << 18) /* dst scatter, !FIX */
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#define DWC_CTLL_FC_M2M (0 << 20) /* mem-to-mem */
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#define DWC_CTLL_FC_M2P (1 << 20) /* mem-to-periph */
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#define DWC_CTLL_FC_P2M (2 << 20) /* periph-to-mem */
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#define DWC_CTLL_FC_P2P (3 << 20) /* periph-to-periph */
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/* plus 4 transfer types for peripheral-as-flow-controller */
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#define DWC_CTLL_DMS(n) ((n)<<23) /* dst master select */
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#define DWC_CTLL_SMS(n) ((n)<<25) /* src master select */
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#define DWC_CTLL_LLP_D_EN (1 << 27) /* dest block chain */
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#define DWC_CTLL_LLP_S_EN (1 << 28) /* src block chain */
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/* Bitfields in CTL_HI */
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#define DWC_CTLH_DONE 0x00001000
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#define DWC_CTLH_BLOCK_TS_MASK 0x00000fff
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/* Bitfields in CFG_LO. Platform-configurable bits are in <linux/dw_dmac.h> */
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#define DWC_CFGL_CH_SUSP (1 << 8) /* pause xfer */
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#define DWC_CFGL_FIFO_EMPTY (1 << 9) /* pause xfer */
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#define DWC_CFGL_HS_DST (1 << 10) /* handshake w/dst */
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#define DWC_CFGL_HS_SRC (1 << 11) /* handshake w/src */
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#define DWC_CFGL_MAX_BURST(x) ((x) << 20)
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#define DWC_CFGL_RELOAD_SAR (1 << 30)
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#define DWC_CFGL_RELOAD_DAR (1 << 31)
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/* Bitfields in CFG_HI. Platform-configurable bits are in <linux/dw_dmac.h> */
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#define DWC_CFGH_DS_UPD_EN (1 << 5)
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#define DWC_CFGH_SS_UPD_EN (1 << 6)
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/* Bitfields in SGR */
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#define DWC_SGR_SGI(x) ((x) << 0)
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#define DWC_SGR_SGC(x) ((x) << 20)
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/* Bitfields in DSR */
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#define DWC_DSR_DSI(x) ((x) << 0)
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#define DWC_DSR_DSC(x) ((x) << 20)
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/* Bitfields in CFG */
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#define DW_CFG_DMA_EN (1 << 0)
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#define DW_REGLEN 0x400
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struct dw_dma_chan {
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struct dma_chan chan;
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void __iomem *ch_regs;
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u8 mask;
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spinlock_t lock;
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/* these other elements are all protected by lock */
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dma_cookie_t completed;
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struct list_head active_list;
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struct list_head queue;
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struct list_head free_list;
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struct dw_dma_slave *dws;
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unsigned int descs_allocated;
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};
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static inline struct dw_dma_chan_regs __iomem *
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__dwc_regs(struct dw_dma_chan *dwc)
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{
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return dwc->ch_regs;
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}
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#define channel_readl(dwc, name) \
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__raw_readl(&(__dwc_regs(dwc)->name))
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#define channel_writel(dwc, name, val) \
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__raw_writel((val), &(__dwc_regs(dwc)->name))
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static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
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{
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return container_of(chan, struct dw_dma_chan, chan);
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}
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struct dw_dma {
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struct dma_device dma;
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void __iomem *regs;
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struct tasklet_struct tasklet;
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struct clk *clk;
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u8 all_chan_mask;
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struct dw_dma_chan chan[0];
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};
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static inline struct dw_dma_regs __iomem *__dw_regs(struct dw_dma *dw)
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{
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return dw->regs;
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}
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#define dma_readl(dw, name) \
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__raw_readl(&(__dw_regs(dw)->name))
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#define dma_writel(dw, name, val) \
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__raw_writel((val), &(__dw_regs(dw)->name))
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#define channel_set_bit(dw, reg, mask) \
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dma_writel(dw, reg, ((mask) << 8) | (mask))
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#define channel_clear_bit(dw, reg, mask) \
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dma_writel(dw, reg, ((mask) << 8) | 0)
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static inline struct dw_dma *to_dw_dma(struct dma_device *ddev)
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{
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return container_of(ddev, struct dw_dma, dma);
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}
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/* LLI == Linked List Item; a.k.a. DMA block descriptor */
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struct dw_lli {
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/* values that are not changed by hardware */
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dma_addr_t sar;
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dma_addr_t dar;
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dma_addr_t llp; /* chain to next lli */
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u32 ctllo;
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/* values that may get written back: */
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u32 ctlhi;
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/* sstat and dstat can snapshot peripheral register state.
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* silicon config may discard either or both...
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*/
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u32 sstat;
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u32 dstat;
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};
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struct dw_desc {
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/* FIRST values the hardware uses */
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struct dw_lli lli;
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/* THEN values for driver housekeeping */
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struct list_head desc_node;
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struct dma_async_tx_descriptor txd;
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size_t len;
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};
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static inline struct dw_desc *
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txd_to_dw_desc(struct dma_async_tx_descriptor *txd)
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{
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return container_of(txd, struct dw_desc, txd);
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}
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@ -30,4 +30,20 @@
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#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
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#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
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/*
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* DMAC peripheral hardware handshaking interfaces, used with dw_dmac
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*/
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#define DMAC_MCI_RX 0
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#define DMAC_MCI_TX 1
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#define DMAC_DAC_TX 2
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#define DMAC_AC97_A_RX 3
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#define DMAC_AC97_A_TX 4
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#define DMAC_AC97_B_RX 5
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#define DMAC_AC97_B_TX 6
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#define DMAC_DMAREQ_0 7
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#define DMAC_DMAREQ_1 8
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#define DMAC_DMAREQ_2 9
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#define DMAC_DMAREQ_3 10
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#endif /* __ASM_ARCH_AT32AP700X_H__ */
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@ -0,0 +1,62 @@
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/*
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* Driver for the Synopsys DesignWare DMA Controller (aka DMACA on
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* AVR32 systems.)
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef DW_DMAC_H
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#define DW_DMAC_H
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#include <linux/dmaengine.h>
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/**
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* struct dw_dma_platform_data - Controller configuration parameters
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* @nr_channels: Number of channels supported by hardware (max 8)
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*/
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struct dw_dma_platform_data {
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unsigned int nr_channels;
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};
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/**
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* struct dw_dma_slave - Controller-specific information about a slave
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* @slave: Generic information about the slave
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* @ctl_lo: Platform-specific initializer for the CTL_LO register
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* @cfg_hi: Platform-specific initializer for the CFG_HI register
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* @cfg_lo: Platform-specific initializer for the CFG_LO register
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*/
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struct dw_dma_slave {
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struct dma_slave slave;
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u32 cfg_hi;
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u32 cfg_lo;
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};
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/* Platform-configurable bits in CFG_HI */
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#define DWC_CFGH_FCMODE (1 << 0)
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#define DWC_CFGH_FIFO_MODE (1 << 1)
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#define DWC_CFGH_PROTCTL(x) ((x) << 2)
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#define DWC_CFGH_SRC_PER(x) ((x) << 7)
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#define DWC_CFGH_DST_PER(x) ((x) << 11)
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/* Platform-configurable bits in CFG_LO */
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#define DWC_CFGL_PRIO(x) ((x) << 5) /* priority */
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#define DWC_CFGL_LOCK_CH_XFER (0 << 12) /* scope of LOCK_CH */
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#define DWC_CFGL_LOCK_CH_BLOCK (1 << 12)
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#define DWC_CFGL_LOCK_CH_XACT (2 << 12)
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#define DWC_CFGL_LOCK_BUS_XFER (0 << 14) /* scope of LOCK_BUS */
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#define DWC_CFGL_LOCK_BUS_BLOCK (1 << 14)
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#define DWC_CFGL_LOCK_BUS_XACT (2 << 14)
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#define DWC_CFGL_LOCK_CH (1 << 15) /* channel lockout */
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#define DWC_CFGL_LOCK_BUS (1 << 16) /* busmaster lockout */
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#define DWC_CFGL_HS_DST_POL (1 << 18) /* dst handshake active low */
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#define DWC_CFGL_HS_SRC_POL (1 << 19) /* src handshake active low */
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static inline struct dw_dma_slave *to_dw_dma_slave(struct dma_slave *slave)
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{
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return container_of(slave, struct dw_dma_slave, slave);
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}
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#endif /* DW_DMAC_H */
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