dect: coa: write BMC configuration when setting channel mode

Write the BMC configuration when setting the channel mode. This allows
to reserve memory for only a single configuration for both RX and TX.

Additionally it will in the future be used to configure S-field error
parameters dynamically.

Signed-off-by: Patrick McHardy <kaber@trash.net>

drivers/dect/coa/sc1442x.c

@@ -63,8 +63,7 @@
  * 0x0e - 0x35:		B-Field		B-Field
  *
  * 0x3a - 0x3e:		Radio Cfg	Radio Cfg
- * 0x40 - 0x47:				BMC TX Cfg
+ * 0x40 - 0x47:		BMC Ctrl	BMC Ctrl
- * 0x48 - 0x4f:		BMC RX Cfg
  * 0x50 - 0x5f:		DCS IV/Key	DCS IV/Key
  * 0x70 - 0x7b:		DCS state	DCS state
  */
@@ -591,6 +590,42 @@ static void sc1442x_lock(const struct dect_transceiver *trx, u8 slot)
 	sc1442x_unlock_mem(dev);
 }
 
+static void sc1442x_write_bmc_config(const struct coa_device *dev,
+				     u8 slot, bool tx)
+{
+	u16 off;
+	u8 cfg;
+
+	off = sc1442x_slot_offset(slot) + BMC_CTRL;
+
+	cfg  = 2 << SC1442X_BC0_S_ERR_SHIFT;
+	cfg |= SC1442X_BC0_INV_TDO;
+	cfg |= SC1442X_BC0_SENS_A;
+	if (slot < 12 && !tx)
+		cfg |= SC1442X_BC0_PP_MODE;
+	sc1442x_dwriteb(dev, off + 0, cfg);
+
+	/* S-field error mask */
+	sc1442x_dwriteb(dev, off + 1, 0);
+	/* S-field sliding window error mask */
+	sc1442x_dwriteb(dev, off + 2, 0x3f);
+
+	/* DAC output */
+	sc1442x_dwriteb(dev, off + 3, 0);
+
+	cfg  = SC1442X_BC4_ADP;
+	cfg |= 0xf & SC1442X_BC4_WIN_MASK;
+	cfg |= 0x80;
+	sc1442x_dwriteb(dev, off + 4, cfg);
+
+	cfg  = SC1442X_BC5_DO_FR;
+	cfg |= tx ? SC1442X_BC5_TDO_DIGITAL : SC1442X_BC5_TDO_POWER_DOWN;
+	sc1442x_dwriteb(dev, off + 5, cfg);
+
+	/* Frame number */
+	sc1442x_dwriteb(dev, off + 6, 0);
+}
+
 static void sc1442x_set_mode(const struct dect_transceiver *trx,
 			     const struct dect_channel_desc *chd,
 			     enum dect_slot_states mode)
@@ -618,6 +653,9 @@ static void sc1442x_set_mode(const struct dect_transceiver *trx,
 		sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
 		sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
 				  sc1442x_rx_funcs[chd->pkt][chd->b_fmt][cipher][sync]);
+
+		sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
+		sc1442x_write_bmc_config(dev, slot, false);
 		break;
 	case DECT_SLOT_TX:
 		sc1442x_write_cmd(dev, slottable[prev] + 0, BK_C,
@@ -626,6 +664,9 @@ static void sc1442x_set_mode(const struct dect_transceiver *trx,
 		sc1442x_write_cmd(dev, slottable[slot] + 0, WT, 1);
 		sc1442x_write_cmd(dev, slottable[slot] + 1, JMP,
 				  sc1442x_tx_funcs[chd->pkt][chd->b_fmt][cipher]);
+
+		sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
+		sc1442x_write_bmc_config(dev, slot, true);
 		break;
 	}
 	sc1442x_unlock_mem(dev);
@@ -672,7 +713,7 @@ static void sc1442x_tx(const struct dect_transceiver *trx, struct sk_buff *skb)
 	sc1442x_to_dmem(dev, off + SD_PREAMBLE_OFF,
 			skb_mac_header(skb), skb->mac_len);
 	sc1442x_to_dmem(dev, off + SD_DATA_OFF, skb->data, skb->len);
-	sc1442x_dwriteb(dev, off + BMC_TX_CTRL + BMC_CTRL_MFR_OFF, cb->frame);
+	sc1442x_dwriteb(dev, off + BMC_CTRL + BMC_CTRL_MFR_OFF, cb->frame);
 
 	/* Init DCS for slots in the first half frame */
 	if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
@@ -835,7 +876,7 @@ out:
 	dect_transceiver_record_rssi(event, slot, rssi);
 
 	/* Update frame number for next reception */
-	sc1442x_dwriteb(dev, off + BMC_RX_CTRL + BMC_CTRL_MFR_OFF, framenum + 1);
+	sc1442x_dwriteb(dev, off + BMC_CTRL + BMC_CTRL_MFR_OFF, framenum + 1);
 
 	/* Init DCS for slots in the first half frame */
 	if (ts->flags & DECT_SLOT_CIPHER && slot < DECT_HALF_FRAME_SIZE)
@@ -879,47 +920,12 @@ out:
 }
 EXPORT_SYMBOL_GPL(sc1442x_interrupt);
 
-static void sc1442x_write_bmc_config(const struct coa_device *dev,
-				     u16 off, bool pp, bool tx)
-{
-	u8 cfg;
-
-	cfg  = 2 << SC1442X_BC0_S_ERR_SHIFT;
-	cfg |= SC1442X_BC0_INV_TDO;
-	cfg |= SC1442X_BC0_SENS_A;
-	if (pp && !tx)
-		cfg |= SC1442X_BC0_PP_MODE;
-	sc1442x_dwriteb(dev, off + 0, cfg);
-
-	/* S-field error mask */
-	sc1442x_dwriteb(dev, off + 1, 0);
-	/* S-field sliding window error mask */
-	sc1442x_dwriteb(dev, off + 2, 0x3f);
-
-	/* DAC output */
-	sc1442x_dwriteb(dev, off + 3, 0);
-
-	cfg  = SC1442X_BC4_ADP;
-	cfg |= 0xf & SC1442X_BC4_WIN_MASK;
-	cfg |= 0x80;
-	sc1442x_dwriteb(dev, off + 4, cfg);
-
-	cfg  = SC1442X_BC5_DO_FR;
-	cfg |= tx ? SC1442X_BC5_TDO_DIGITAL : SC1442X_BC5_TDO_POWER_DOWN;
-	sc1442x_dwriteb(dev, off + 5, cfg);
-
-	/* Frame number */
-	sc1442x_dwriteb(dev, off + 6, 0);
-}
-
 static void sc1442x_init_slot(const struct coa_device *dev, u8 slot)
 {
 	u16 off;
 
 	sc1442x_switch_to_bank(dev, sc1442x_slot_bank(slot));
 	off = sc1442x_slot_offset(slot);
-	sc1442x_write_bmc_config(dev, off + BMC_TX_CTRL, slot < 12, true);
-	sc1442x_write_bmc_config(dev, off + BMC_RX_CTRL, slot < 12, false);
 	dev->radio_ops->rx_init(dev, off);
 	dev->radio_ops->tx_init(dev, off);
 }
@@ -987,7 +993,7 @@ int sc1442x_init_device(struct coa_device *dev)
 	for (i = 1; i < SC1442X_CC_SIZE; i++)
 		sc1442x_dwriteb(dev, DIP_CC_INIT + i, 0);
 
-	sc1442x_write_bmc_config(dev, BMC_CTRL_INIT, false, false);
+	sc1442x_write_bmc_config(dev, 0, false);
 	for (slot = 0; slot < DECT_FRAME_SIZE; slot += 2)
 		sc1442x_init_slot(dev, slot);
 

drivers/dect/coa/sc1442x_firmware.asm

@@ -34,8 +34,6 @@ BANK6_HIGH	EQU	0xd0
 BANK7_LOW	EQU	0xe0
 BANK7_HIGH	EQU	0xf0
 
-BMC_CTRL_INIT	EQU	0x00
-
 ; Codec Control
 DIP_CC_INIT	EQU	0x10
 
@@ -44,8 +42,7 @@ RF_DESC		EQU	0x3a
 
 ; BMC control information
 BMC_CTRL_SIZE	EQU	7
-BMC_TX_CTRL	EQU	0x40
+BMC_CTRL	EQU	0x40
-BMC_RX_CTRL	EQU	0x48
 
 ; (multi) frame number for scambler and DCS
 BMC_CTRL_MFR_OFF EQU	6
@@ -225,7 +222,7 @@ label_58:	B_RST
 ; (93 bits total)
 ;
 Receive:	B_RST
-		B_RC	BMC_RX_CTRL
+		B_RC	BMC_CTRL
 		WT	BMC_CTRL_SIZE + 1
 		P_LDH	PB_RX_ON
 		P_LDL	PB_RSSI		; enable RSSI measurement
@@ -247,7 +244,7 @@ ClockSyncOff:	P_SC	0x00		;						| p:  30	S: 46
 		RTN			; Return					| p:  93	A: 61
 
 ReceiveSync:	B_RST
-		B_RC	BMC_RX_CTRL
+		B_RC	BMC_CTRL
 		WT	BMC_CTRL_SIZE + 1
 		P_LDH	PB_RX_ON
 		P_LDL	PB_RSSI		; enable RSSI measurement
@@ -285,7 +282,7 @@ ReceiveEnd:	P_LDH	PB_RSSI		;						|
 Transmit:	P_LDH	0x00		;
 		WT	40		;
 		B_RST			;
-		B_RC	BMC_TX_CTRL	;
+		B_RC	BMC_CTRL	;
 		WNT	1		; Wait until beginning of slot
 		B_ST	0x00		; Start transmission of S-field data		|
 		WT	1		; Wait one bit					| p: -8		S:  0
@@ -411,7 +408,7 @@ InitDIP:	;B_RST
 		BK_C	BANK0_LOW
 		C_LD	DIP_CC_INIT
 		WT	10
-		B_RC	BMC_CTRL_INIT
+		B_RC	BMC_CTRL
 		WT	BMC_CTRL_SIZE + 1
 		B_RST
 		;C_ON
@@ -424,7 +421,7 @@ RFStart:	BR	SyncInit
 ;-------------------------------------------------------------
 
 		SHARED	DIP_CC_INIT,RF_DESC
-		SHARED	BMC_CTRL_INIT,BMC_RX_CTRL,BMC_TX_CTRL,BMC_CTRL_MFR_OFF
+		SHARED	BMC_CTRL,BMC_CTRL_MFR_OFF
 		SHARED	SD_RSSI_OFF,SD_CSUM_OFF,SD_PREAMBLE_OFF,SD_DATA_OFF
 
 		SHARED	SlotTable

drivers/dect/coa/sc1442x_firmware.c

@@ -33,13 +33,13 @@ const unsigned char sc1442x_firmware[] = {
 	0x02, 0xa8, 0x01, 0x67, 0x39, 0x00, 0x09, 0x06,
 	0x20, 0x00, 0xec, 0x50, 0x09, 0x05, 0x08, 0x01,
 	0x04, 0x00, 0x39, 0x00, 0x09, 0x06, 0x20, 0x00,
-	0xec, 0x50, 0x04, 0x00, 0x20, 0x00, 0x33, 0x48,
+	0xec, 0x50, 0x04, 0x00, 0x20, 0x00, 0x33, 0x40,
 	0x09, 0x08, 0xed, 0x40, 0xec, 0x01, 0x09, 0x19,
 	0x08, 0x01, 0x09, 0x08, 0x27, 0x00, 0xea, 0x20,
 	0xed, 0x02, 0x09, 0x05, 0x29, 0x00, 0x2c, 0x00,
 	0x09, 0x0c, 0xec, 0x02, 0x09, 0x20, 0xea, 0x00,
 	0x3f, 0x06, 0x09, 0x3e, 0x04, 0x00, 0x20, 0x00,
-	0x33, 0x48, 0x09, 0x08, 0xed, 0x40, 0xec, 0x01,
+	0x33, 0x40, 0x09, 0x08, 0xed, 0x40, 0xec, 0x01,
 	0x09, 0x19, 0x08, 0x01, 0x09, 0x08, 0x27, 0x00,
 	0xea, 0x20, 0xed, 0x02, 0x09, 0x05, 0x29, 0x00,
 	0x2c, 0x00, 0x09, 0x0c, 0xec, 0x02, 0x09, 0x20,
@@ -68,6 +68,6 @@ const unsigned char sc1442x_firmware[] = {
 	0x03, 0xed, 0x20, 0x00, 0x6b, 0x00, 0x08, 0x17,
 	0x01, 0xdf, 0x08, 0x17, 0xea, 0x00, 0x02, 0x38,
 	0x61, 0x00, 0x08, 0x16, 0x01, 0xdf, 0x0f, 0x00,
-	0xfa, 0x10, 0x09, 0x0a, 0x33, 0x00, 0x09, 0x08,
+	0xfa, 0x10, 0x09, 0x0a, 0x33, 0x40, 0x09, 0x08,
 	0x20, 0x00, 0x09, 0x0a, 0xe9, 0x00, 0xe8, 0x04,
 	0x62, 0x00, 0x0b, 0x00, 0x01, 0xde};

drivers/dect/coa/sc1442x_firmware.h

@@ -5,9 +5,7 @@ extern const unsigned char sc1442x_firmware[510];
 
 #define DIP_CC_INIT 0x10
 #define RF_DESC 0x3A
-#define BMC_CTRL_INIT 0x0
+#define BMC_CTRL 0x40
-#define BMC_RX_CTRL 0x48
-#define BMC_TX_CTRL 0x40
 #define BMC_CTRL_MFR_OFF 0x6
 #define SD_RSSI_OFF 0x0
 #define SD_CSUM_OFF 0x1