pinctrl: mvebu: dove pinctrl driver
This patch adds a SoC specific pinctrl driver for Marvell Dove SoCs plus DT binding documentation. This driver will use the mvebu pinctrl driver core. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This commit is contained in:
Sebastian Hesselbarth
Jason Cooper
parent
7e8d941567
commit
c9f95cedfe
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@ -0,0 +1,72 @@
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* Marvell Dove SoC pinctrl driver for mpp
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Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
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part and usage.
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Required properties:
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- compatible: "marvell,dove-pinctrl"
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- clocks: (optional) phandle of pdma clock
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Available mpp pins/groups and functions:
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Note: brackets (x) are not part of the mpp name for marvell,function and given
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only for more detailed description in this document.
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name pins functions
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================================================================================
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mpp0 0 gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
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mpp1 1 gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
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mpp2 2 gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
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uart1(rts)
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mpp3 3 gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
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uart1(cts), lcd-spi(cs1)
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mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
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mpp5 5 gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
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mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
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mpp7 7 gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
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mpp8 8 gpio, pmu, watchdog(rstout)
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mpp9 9 gpio, pmu, pex1(clkreq)
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mpp10 10 gpio, pmu, ssp(sclk)
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mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
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sdio1(ledctrl), pex0(clkreq)
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mpp12 12 gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
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mpp13 13 gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
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ssp(extclk)
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mpp14 14 gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
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mpp15 15 gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
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mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
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mpp17 17 gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
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ac97-1(sysclko)
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mpp18 18 gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
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mpp19 19 gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
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mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
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ac97(sysclko)
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mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
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uart1(cts), ssp(sfrm)
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mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
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lcd-spi(mosi), uart1(cts), ssp(txd)
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mpp23 23 gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
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lcd-spi(sck), ssp(sclk)
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mpp_camera 24-39 gpio, camera
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mpp_sdio0 40-45 gpio, sdio0
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mpp_sdio1 46-51 gpio, sdio1
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mpp_audio1 52-57 gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
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ssp/twsi
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mpp_spi0 58-61 gpio, spi0
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mpp_uart1 62-63 gpio, uart1
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mpp_nand 64-71 gpo, nand
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audio0 - i2s, ac97
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twsi - none, opt1, opt2, opt3
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Notes:
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* group "mpp_audio1" allows the following functions and gpio pins:
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- gpio : gpio on pins 52-57
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- i2s1/spdifo : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
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- i2s1 : audio1 i2s on pins 52-55, gpio on pins 56,57
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- spdifo : spdifo on pin 57, gpio on pins 52-55
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- twsi : twsi on pins 56,57, gpio on pins 52-55
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- ssp/spdifo : ssp on pins 52-55, spdifo on pin 57, no gpios
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- ssp : ssp on pins 52-55, gpio on pins 56,57
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- ssp/twsi : ssp on pins 52-55, twsi on pins 56,57, no gpios
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* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
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audio0 pins.
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* group "twsi" internally muxes twsi controller to the dedicated or option pins.
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@ -151,6 +151,10 @@ config PINCTRL_MVEBU
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select PINMUX
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select PINCONF
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config PINCTRL_DOVE
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bool
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select PINCTRL_MVEBU
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source "drivers/pinctrl/spear/Kconfig"
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endmenu
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@ -30,5 +30,6 @@ obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
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obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
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obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
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obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
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obj-$(CONFIG_PINCTRL_DOVE) += pinctrl-dove.o
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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@ -0,0 +1,620 @@
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/*
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* Marvell Dove pinctrl driver based on mvebu pinctrl core
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*
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* Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/bitops.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-mvebu.h"
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#define DOVE_SB_REGS_VIRT_BASE 0xfde00000
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#define DOVE_MPP_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
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#define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
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#define DOVE_AU0_AC97_SEL BIT(16)
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#define DOVE_GLOBAL_CONFIG_1 (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
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#define DOVE_TWSI_ENABLE_OPTION1 BIT(7)
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#define DOVE_GLOBAL_CONFIG_2 (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
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#define DOVE_TWSI_ENABLE_OPTION2 BIT(20)
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#define DOVE_TWSI_ENABLE_OPTION3 BIT(21)
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#define DOVE_TWSI_OPTION3_GPIO BIT(22)
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#define DOVE_SSP_CTRL_STATUS_1 (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
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#define DOVE_SSP_ON_AU1 BIT(0)
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#define DOVE_MPP_GENERAL_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
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#define DOVE_AU1_SPDIFO_GPIO_EN BIT(1)
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#define DOVE_NAND_GPIO_EN BIT(0)
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#define DOVE_GPIO_LO_VIRT_BASE (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
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#define DOVE_MPP_CTRL4_VIRT_BASE (DOVE_GPIO_LO_VIRT_BASE + 0x40)
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#define DOVE_SPI_GPIO_SEL BIT(5)
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#define DOVE_UART1_GPIO_SEL BIT(4)
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#define DOVE_AU1_GPIO_SEL BIT(3)
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#define DOVE_CAM_GPIO_SEL BIT(2)
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#define DOVE_SD1_GPIO_SEL BIT(1)
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#define DOVE_SD0_GPIO_SEL BIT(0)
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#define MPPS_PER_REG 8
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#define MPP_BITS 4
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#define MPP_MASK 0xf
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#define CONFIG_PMU BIT(4)
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static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
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unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
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unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
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unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
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if (pmu & (1 << ctrl->pid))
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*config = CONFIG_PMU;
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else
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*config = (mpp >> shift) & MPP_MASK;
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return 0;
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}
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static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
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unsigned long config)
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{
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unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
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unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
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unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
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unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
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if (config == CONFIG_PMU)
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writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
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else {
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writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
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mpp &= ~(MPP_MASK << shift);
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mpp |= config << shift;
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writel(mpp, DOVE_MPP_VIRT_BASE + off);
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}
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return 0;
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}
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static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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unsigned long mask;
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switch (ctrl->pid) {
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case 24: /* mpp_camera */
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mask = DOVE_CAM_GPIO_SEL;
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break;
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case 40: /* mpp_sdio0 */
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mask = DOVE_SD0_GPIO_SEL;
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break;
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case 46: /* mpp_sdio1 */
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mask = DOVE_SD1_GPIO_SEL;
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break;
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case 58: /* mpp_spi0 */
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mask = DOVE_SPI_GPIO_SEL;
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break;
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case 62: /* mpp_uart1 */
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mask = DOVE_UART1_GPIO_SEL;
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break;
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default:
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return -EINVAL;
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}
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*config = ((mpp4 & mask) != 0);
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return 0;
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}
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static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
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unsigned long config)
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{
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unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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unsigned long mask;
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switch (ctrl->pid) {
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case 24: /* mpp_camera */
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mask = DOVE_CAM_GPIO_SEL;
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break;
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case 40: /* mpp_sdio0 */
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mask = DOVE_SD0_GPIO_SEL;
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break;
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case 46: /* mpp_sdio1 */
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mask = DOVE_SD1_GPIO_SEL;
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break;
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case 58: /* mpp_spi0 */
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mask = DOVE_SPI_GPIO_SEL;
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break;
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case 62: /* mpp_uart1 */
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mask = DOVE_UART1_GPIO_SEL;
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break;
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default:
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return -EINVAL;
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}
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mpp4 &= ~mask;
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if (config)
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mpp4 |= mask;
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writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
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return 0;
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}
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static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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*config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
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return 0;
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}
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static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
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unsigned long config)
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{
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unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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gmpp &= ~DOVE_NAND_GPIO_EN;
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if (config)
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gmpp |= DOVE_NAND_GPIO_EN;
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writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
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return 0;
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}
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static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
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*config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
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return 0;
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}
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static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
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unsigned long config)
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{
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unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
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pmu &= ~DOVE_AU0_AC97_SEL;
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if (config)
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pmu |= DOVE_AU0_AC97_SEL;
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writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
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return 0;
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}
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static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
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unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
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*config = 0;
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if (mpp4 & DOVE_AU1_GPIO_SEL)
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*config |= BIT(3);
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if (sspc1 & DOVE_SSP_ON_AU1)
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*config |= BIT(2);
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if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
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*config |= BIT(1);
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if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
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*config |= BIT(0);
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/* SSP/TWSI only if I2S1 not set*/
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if ((*config & BIT(3)) == 0)
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*config &= ~(BIT(2) | BIT(0));
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/* TWSI only if SPDIFO not set*/
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if ((*config & BIT(1)) == 0)
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*config &= ~BIT(0);
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return 0;
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}
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static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
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unsigned long config)
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{
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unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
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unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
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unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
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unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
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if (config & BIT(0))
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gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
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if (config & BIT(1))
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gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
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if (config & BIT(2))
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sspc1 |= DOVE_SSP_ON_AU1;
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if (config & BIT(3))
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mpp4 |= DOVE_AU1_GPIO_SEL;
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writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
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writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
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writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
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writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
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return 0;
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}
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/* mpp[52:57] gpio pins depend heavily on current config;
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* gpio_req does not try to mux in gpio capabilities to not
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* break other functions. If you require all mpps as gpio
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* enforce gpio setting by pinctrl mapping.
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*/
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static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
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{
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unsigned long config;
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dove_audio1_ctrl_get(ctrl, &config);
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switch (config) {
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case 0x02: /* i2s1 : gpio[56:57] */
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case 0x0e: /* ssp : gpio[56:57] */
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if (pid >= 56)
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return 0;
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return -ENOTSUPP;
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case 0x08: /* spdifo : gpio[52:55] */
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case 0x0b: /* twsi : gpio[52:55] */
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if (pid <= 55)
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return 0;
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return -ENOTSUPP;
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case 0x0a: /* all gpio */
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return 0;
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/* 0x00 : i2s1/spdifo : no gpio */
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/* 0x0c : ssp/spdifo : no gpio */
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/* 0x0f : ssp/twsi : no gpio */
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}
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return -ENOTSUPP;
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}
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/* mpp[52:57] has gpio pins capable of in and out */
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static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
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bool input)
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{
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if (pid < 52 || pid > 57)
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return -ENOTSUPP;
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return 0;
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}
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static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
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unsigned long *config)
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{
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unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
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unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
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*config = 0;
|
||||
if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
|
||||
*config = 1;
|
||||
else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
|
||||
*config = 2;
|
||||
else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
|
||||
*config = 3;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
|
||||
unsigned long config)
|
||||
{
|
||||
unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
|
||||
unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
|
||||
|
||||
gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
|
||||
gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
|
||||
|
||||
switch (config) {
|
||||
case 1:
|
||||
gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
|
||||
break;
|
||||
case 2:
|
||||
gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
|
||||
break;
|
||||
case 3:
|
||||
gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
|
||||
break;
|
||||
}
|
||||
|
||||
writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
|
||||
writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
|
||||
MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
|
||||
MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
|
||||
MPP_REG_CTRL(16, 23),
|
||||
MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
|
||||
MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
|
||||
MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
|
||||
MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
|
||||
MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
|
||||
MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
|
||||
MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
|
||||
MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
|
||||
MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
|
||||
};
|
||||
|
||||
static struct mvebu_mpp_mode dove_mpp_modes[] = {
|
||||
MPP_MODE(0,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart2", "rts"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "cd"),
|
||||
MPP_FUNCTION(0x0f, "lcd0", "pwm"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(1,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart2", "cts"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "wp"),
|
||||
MPP_FUNCTION(0x0f, "lcd1", "pwm"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(2,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "sata", "prsnt"),
|
||||
MPP_FUNCTION(0x02, "uart2", "txd"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "buspwr"),
|
||||
MPP_FUNCTION(0x04, "uart1", "rts"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(3,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "sata", "act"),
|
||||
MPP_FUNCTION(0x02, "uart2", "rxd"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
|
||||
MPP_FUNCTION(0x04, "uart1", "cts"),
|
||||
MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(4,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "rts"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "cd"),
|
||||
MPP_FUNCTION(0x04, "spi1", "miso"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(5,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "cts"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "wp"),
|
||||
MPP_FUNCTION(0x04, "spi1", "cs"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(6,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "txd"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "buspwr"),
|
||||
MPP_FUNCTION(0x04, "spi1", "mosi"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(7,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "rxd"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
|
||||
MPP_FUNCTION(0x04, "spi1", "sck"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(8,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "watchdog", "rstout"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(9,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x05, "pex1", "clkreq"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(10,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x05, "ssp", "sclk"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(11,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "sata", "prsnt"),
|
||||
MPP_FUNCTION(0x02, "sata-1", "act"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
|
||||
MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
|
||||
MPP_FUNCTION(0x05, "pex0", "clkreq"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(12,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "sata", "act"),
|
||||
MPP_FUNCTION(0x02, "uart2", "rts"),
|
||||
MPP_FUNCTION(0x03, "audio0", "extclk"),
|
||||
MPP_FUNCTION(0x04, "sdio1", "cd"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(13,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart2", "cts"),
|
||||
MPP_FUNCTION(0x03, "audio1", "extclk"),
|
||||
MPP_FUNCTION(0x04, "sdio1", "wp"),
|
||||
MPP_FUNCTION(0x05, "ssp", "extclk"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(14,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart2", "txd"),
|
||||
MPP_FUNCTION(0x04, "sdio1", "buspwr"),
|
||||
MPP_FUNCTION(0x05, "ssp", "rxd"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(15,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart2", "rxd"),
|
||||
MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
|
||||
MPP_FUNCTION(0x05, "ssp", "sfrm"),
|
||||
MPP_FUNCTION(0x10, "pmu", NULL)),
|
||||
MPP_MODE(16,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "rts"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "cd"),
|
||||
MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
|
||||
MPP_FUNCTION(0x05, "ac97", "sdi1")),
|
||||
MPP_MODE(17,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
|
||||
MPP_FUNCTION(0x02, "uart3", "cts"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "wp"),
|
||||
MPP_FUNCTION(0x04, "twsi", "sda"),
|
||||
MPP_FUNCTION(0x05, "ac97", "sdi2")),
|
||||
MPP_MODE(18,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "txd"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "buspwr"),
|
||||
MPP_FUNCTION(0x04, "lcd0", "pwm"),
|
||||
MPP_FUNCTION(0x05, "ac97", "sdi3")),
|
||||
MPP_MODE(19,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "uart3", "rxd"),
|
||||
MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
|
||||
MPP_FUNCTION(0x04, "twsi", "sck")),
|
||||
MPP_MODE(20,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "ac97", "sysclko"),
|
||||
MPP_FUNCTION(0x02, "lcd-spi", "miso"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "cd"),
|
||||
MPP_FUNCTION(0x05, "sdio0", "cd"),
|
||||
MPP_FUNCTION(0x06, "spi1", "miso")),
|
||||
MPP_MODE(21,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "uart1", "rts"),
|
||||
MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "wp"),
|
||||
MPP_FUNCTION(0x04, "ssp", "sfrm"),
|
||||
MPP_FUNCTION(0x05, "sdio0", "wp"),
|
||||
MPP_FUNCTION(0x06, "spi1", "cs")),
|
||||
MPP_MODE(22,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x01, "uart1", "cts"),
|
||||
MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "buspwr"),
|
||||
MPP_FUNCTION(0x04, "ssp", "txd"),
|
||||
MPP_FUNCTION(0x05, "sdio0", "buspwr"),
|
||||
MPP_FUNCTION(0x06, "spi1", "mosi")),
|
||||
MPP_MODE(23,
|
||||
MPP_FUNCTION(0x00, "gpio", NULL),
|
||||
MPP_FUNCTION(0x02, "lcd-spi", "sck"),
|
||||
MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
|
||||
MPP_FUNCTION(0x04, "ssp", "sclk"),
|
||||
MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
|
||||
MPP_FUNCTION(0x06, "spi1", "sck")),
|
||||
MPP_MODE(24,
|
||||
MPP_FUNCTION(0x00, "camera", NULL),
|
||||
MPP_FUNCTION(0x01, "gpio", NULL)),
|
||||
MPP_MODE(40,
|
||||
MPP_FUNCTION(0x00, "sdio0", NULL),
|
||||
MPP_FUNCTION(0x01, "gpio", NULL)),
|
||||
MPP_MODE(46,
|
||||
MPP_FUNCTION(0x00, "sdio1", NULL),
|
||||
MPP_FUNCTION(0x01, "gpio", NULL)),
|
||||
MPP_MODE(52,
|
||||
MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
|
||||
MPP_FUNCTION(0x02, "i2s1", NULL),
|
||||
MPP_FUNCTION(0x08, "spdifo", NULL),
|
||||
MPP_FUNCTION(0x0a, "gpio", NULL),
|
||||
MPP_FUNCTION(0x0b, "twsi", NULL),
|
||||
MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
|
||||
MPP_FUNCTION(0x0e, "ssp", NULL),
|
||||
MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
|
||||
MPP_MODE(58,
|
||||
MPP_FUNCTION(0x00, "spi0", NULL),
|
||||
MPP_FUNCTION(0x01, "gpio", NULL)),
|
||||
MPP_MODE(62,
|
||||
MPP_FUNCTION(0x00, "uart1", NULL),
|
||||
MPP_FUNCTION(0x01, "gpio", NULL)),
|
||||
MPP_MODE(64,
|
||||
MPP_FUNCTION(0x00, "nand", NULL),
|
||||
MPP_FUNCTION(0x01, "gpo", NULL)),
|
||||
MPP_MODE(72,
|
||||
MPP_FUNCTION(0x00, "i2s", NULL),
|
||||
MPP_FUNCTION(0x01, "ac97", NULL)),
|
||||
MPP_MODE(73,
|
||||
MPP_FUNCTION(0x00, "twsi-none", NULL),
|
||||
MPP_FUNCTION(0x01, "twsi-opt1", NULL),
|
||||
MPP_FUNCTION(0x02, "twsi-opt2", NULL),
|
||||
MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
|
||||
};
|
||||
|
||||
static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
|
||||
MPP_GPIO_RANGE(0, 0, 0, 32),
|
||||
MPP_GPIO_RANGE(1, 32, 32, 32),
|
||||
MPP_GPIO_RANGE(2, 64, 64, 8),
|
||||
};
|
||||
|
||||
static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
|
||||
.controls = dove_mpp_controls,
|
||||
.ncontrols = ARRAY_SIZE(dove_mpp_controls),
|
||||
.modes = dove_mpp_modes,
|
||||
.nmodes = ARRAY_SIZE(dove_mpp_modes),
|
||||
.gpioranges = dove_mpp_gpio_ranges,
|
||||
.ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
|
||||
.variant = 0,
|
||||
};
|
||||
|
||||
static struct clk *clk;
|
||||
|
||||
static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
|
||||
{ .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
|
||||
{ }
|
||||
};
|
||||
|
||||
static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match =
|
||||
of_match_device(dove_pinctrl_of_match, &pdev->dev);
|
||||
pdev->dev.platform_data = match->data;
|
||||
|
||||
/*
|
||||
* General MPP Configuration Register is part of pdma registers.
|
||||
* grab clk to make sure it is ticking.
|
||||
*/
|
||||
clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (!IS_ERR(clk))
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
return mvebu_pinctrl_probe(pdev);
|
||||
}
|
||||
|
||||
static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = mvebu_pinctrl_remove(pdev);
|
||||
if (!IS_ERR(clk))
|
||||
clk_disable_unprepare(clk);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver dove_pinctrl_driver = {
|
||||
.driver = {
|
||||
.name = "dove-pinctrl",
|
||||
.owner = THIS_MODULE,
|
||||
.of_match_table = of_match_ptr(dove_pinctrl_of_match),
|
||||
},
|
||||
.probe = dove_pinctrl_probe,
|
||||
.remove = __devexit_p(dove_pinctrl_remove),
|
||||
};
|
||||
|
||||
module_platform_driver(dove_pinctrl_driver);
|
||||
|
||||
MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
|
||||
MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
Reference in New Issue