pinctrl: mvebu: pinctrl driver core
This patch adds a pinctrl driver core for Marvell SoCs plus DT binding documentation. This core driver will be used by SoC family specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net> Conflicts: arch/arm/Kconfig
This commit is contained in:
Sebastian Hesselbarth
Jason Cooper
parent
5b40baee4a
commit
7e8d941567
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@ -0,0 +1,46 @@
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* Marvell SoC pinctrl core driver for mpp
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The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
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(mpp) to a specific function. For each SoC family there is a SoC specific
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driver using this core driver.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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A Marvell SoC pin configuration node is a node of a group of pins which can
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be used for a specific device or function. Each node requires one or more
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mpp pins or group of pins and a mpp function common to all pins.
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Required properties for pinctrl driver:
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- compatible: "marvell,<soc>-pinctrl"
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Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
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Required properties for pin configuration node:
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- marvell,pins: string array of mpp pins or group of pins to be muxed.
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- marvell,function: string representing a function to mux to for all
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marvell,pins given in this pin configuration node. The function has to be
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common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
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valid pin/pin group names and available function names for each SoC.
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Examples:
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uart1: serial@12100 {
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compatible = "ns16550a";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <7>;
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pinctrl-0 = <&pmx_uart1_sw>;
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pinctrl-names = "default";
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};
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pinctrl: pinctrl@d0200 {
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compatible = "marvell,dove-pinctrl";
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reg = <0xd0200 0x20>;
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pmx_uart1_sw: pmx-uart1-sw {
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marvell,pins = "mpp_uart1";
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marvell,function = "uart1";
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};
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};
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@ -568,6 +568,7 @@ config ARCH_MVEBU
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select IRQ_DOMAIN
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select COMMON_CLK
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select PLAT_ORION
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select PINCTRL
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help
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Support for the Marvell SoC Family with device tree support
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@ -145,6 +145,12 @@ config PINCTRL_COH901
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COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
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ports of 8 GPIO pins each.
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config PINCTRL_MVEBU
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bool
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depends on ARCH_MVEBU
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select PINMUX
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select PINCONF
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source "drivers/pinctrl/spear/Kconfig"
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endmenu
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@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
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obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
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obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
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obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
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obj-$(CONFIG_PINCTRL_MVEBU) += pinctrl-mvebu.o
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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@ -0,0 +1,754 @@
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/*
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* Marvell MVEBU pinctrl core driver
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*
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* Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include "core.h"
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#include "pinctrl-mvebu.h"
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#define MPPS_PER_REG 8
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#define MPP_BITS 4
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#define MPP_MASK 0xf
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struct mvebu_pinctrl_function {
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const char *name;
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const char **groups;
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unsigned num_groups;
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};
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struct mvebu_pinctrl_group {
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const char *name;
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struct mvebu_mpp_ctrl *ctrl;
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struct mvebu_mpp_ctrl_setting *settings;
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unsigned num_settings;
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unsigned gid;
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unsigned *pins;
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unsigned npins;
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};
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struct mvebu_pinctrl {
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struct device *dev;
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struct pinctrl_dev *pctldev;
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struct pinctrl_desc desc;
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void __iomem *base;
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struct mvebu_pinctrl_group *groups;
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unsigned num_groups;
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struct mvebu_pinctrl_function *functions;
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unsigned num_functions;
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u8 variant;
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};
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static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
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struct mvebu_pinctrl *pctl, unsigned pid)
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{
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unsigned n;
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for (n = 0; n < pctl->num_groups; n++) {
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if (pid >= pctl->groups[n].pins[0] &&
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pid < pctl->groups[n].pins[0] +
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pctl->groups[n].npins)
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return &pctl->groups[n];
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}
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return NULL;
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}
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static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
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struct mvebu_pinctrl *pctl, const char *name)
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{
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unsigned n;
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for (n = 0; n < pctl->num_groups; n++) {
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if (strcmp(name, pctl->groups[n].name) == 0)
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return &pctl->groups[n];
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}
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return NULL;
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}
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static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
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struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
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unsigned long config)
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{
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unsigned n;
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for (n = 0; n < grp->num_settings; n++) {
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if (config == grp->settings[n].val) {
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if (!pctl->variant || (pctl->variant &
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grp->settings[n].variant))
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return &grp->settings[n];
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}
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}
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return NULL;
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}
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static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
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struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
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const char *name)
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{
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unsigned n;
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for (n = 0; n < grp->num_settings; n++) {
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if (strcmp(name, grp->settings[n].name) == 0) {
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if (!pctl->variant || (pctl->variant &
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grp->settings[n].variant))
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return &grp->settings[n];
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}
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}
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return NULL;
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}
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static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
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struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
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{
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unsigned n;
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for (n = 0; n < grp->num_settings; n++) {
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if (grp->settings[n].flags &
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(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
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if (!pctl->variant || (pctl->variant &
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grp->settings[n].variant))
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return &grp->settings[n];
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}
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}
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return NULL;
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}
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static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
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struct mvebu_pinctrl *pctl, const char *name)
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{
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unsigned n;
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for (n = 0; n < pctl->num_functions; n++) {
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if (strcmp(name, pctl->functions[n].name) == 0)
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return &pctl->functions[n];
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}
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return NULL;
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}
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/*
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* Common mpp pin configuration registers on MVEBU are
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* registers of eight 4-bit values for each mpp setting.
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* Register offset and bit mask are calculated accordingly below.
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*/
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static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
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struct mvebu_pinctrl_group *grp,
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unsigned long *config)
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{
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unsigned pin = grp->gid;
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unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
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unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
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*config = readl(pctl->base + off);
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*config >>= shift;
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*config &= MPP_MASK;
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return 0;
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}
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static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
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struct mvebu_pinctrl_group *grp,
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unsigned long config)
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{
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unsigned pin = grp->gid;
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unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
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unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
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unsigned long reg;
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reg = readl(pctl->base + off);
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reg &= ~(MPP_MASK << shift);
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reg |= (config << shift);
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writel(reg, pctl->base + off);
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return 0;
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}
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static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
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unsigned gid, unsigned long *config)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
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if (!grp->ctrl)
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return -EINVAL;
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if (grp->ctrl->mpp_get)
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return grp->ctrl->mpp_get(grp->ctrl, config);
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return mvebu_common_mpp_get(pctl, grp, config);
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}
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static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
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unsigned gid, unsigned long config)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
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if (!grp->ctrl)
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return -EINVAL;
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if (grp->ctrl->mpp_set)
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return grp->ctrl->mpp_set(grp->ctrl, config);
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return mvebu_common_mpp_set(pctl, grp, config);
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}
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static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned gid)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
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struct mvebu_mpp_ctrl_setting *curr;
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unsigned long config;
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unsigned n;
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if (mvebu_pinconf_group_get(pctldev, gid, &config))
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return;
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curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
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if (curr) {
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seq_printf(s, "current: %s", curr->name);
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if (curr->subname)
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seq_printf(s, "(%s)", curr->subname);
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if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
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seq_printf(s, "(");
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if (curr->flags & MVEBU_SETTING_GPI)
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seq_printf(s, "i");
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if (curr->flags & MVEBU_SETTING_GPO)
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seq_printf(s, "o");
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seq_printf(s, ")");
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}
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} else
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seq_printf(s, "current: UNKNOWN");
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if (grp->num_settings > 1) {
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seq_printf(s, ", available = [");
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for (n = 0; n < grp->num_settings; n++) {
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if (curr == &grp->settings[n])
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continue;
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/* skip unsupported settings for this variant */
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if (pctl->variant &&
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!(pctl->variant & grp->settings[n].variant))
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continue;
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seq_printf(s, " %s", grp->settings[n].name);
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if (grp->settings[n].subname)
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seq_printf(s, "(%s)", grp->settings[n].subname);
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if (grp->settings[n].flags &
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(MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
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seq_printf(s, "(");
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if (grp->settings[n].flags & MVEBU_SETTING_GPI)
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seq_printf(s, "i");
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if (grp->settings[n].flags & MVEBU_SETTING_GPO)
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seq_printf(s, "o");
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seq_printf(s, ")");
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}
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}
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seq_printf(s, " ]");
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}
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return;
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}
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static struct pinconf_ops mvebu_pinconf_ops = {
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.pin_config_group_get = mvebu_pinconf_group_get,
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.pin_config_group_set = mvebu_pinconf_group_set,
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.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
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};
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static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->num_functions;
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}
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static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
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unsigned fid)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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return pctl->functions[fid].name;
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}
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static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
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const char * const **groups,
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unsigned * const num_groups)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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*groups = pctl->functions[fid].groups;
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*num_groups = pctl->functions[fid].num_groups;
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return 0;
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}
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static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
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unsigned gid)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_function *func = &pctl->functions[fid];
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struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
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struct mvebu_mpp_ctrl_setting *setting;
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int ret;
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setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
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func->name);
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if (!setting) {
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dev_err(pctl->dev,
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"unable to find setting %s in group %s\n",
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func->name, func->groups[gid]);
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return -EINVAL;
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}
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ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
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if (ret) {
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dev_err(pctl->dev, "cannot set group %s to %s\n",
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func->groups[gid], func->name);
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return ret;
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}
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return 0;
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}
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static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_group *grp;
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struct mvebu_mpp_ctrl_setting *setting;
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grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
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if (!grp)
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return -EINVAL;
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if (grp->ctrl->mpp_gpio_req)
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return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
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setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
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if (!setting)
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return -ENOTSUPP;
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return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
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}
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static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range, unsigned offset, bool input)
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{
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struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
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struct mvebu_pinctrl_group *grp;
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struct mvebu_mpp_ctrl_setting *setting;
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grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
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if (!grp)
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return -EINVAL;
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if (grp->ctrl->mpp_gpio_dir)
|
||||
return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
|
||||
|
||||
setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
|
||||
if (!setting)
|
||||
return -ENOTSUPP;
|
||||
|
||||
if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
|
||||
(!input && (setting->flags & MVEBU_SETTING_GPO)))
|
||||
return 0;
|
||||
|
||||
return -ENOTSUPP;
|
||||
}
|
||||
|
||||
static struct pinmux_ops mvebu_pinmux_ops = {
|
||||
.get_functions_count = mvebu_pinmux_get_funcs_count,
|
||||
.get_function_name = mvebu_pinmux_get_func_name,
|
||||
.get_function_groups = mvebu_pinmux_get_groups,
|
||||
.gpio_request_enable = mvebu_pinmux_gpio_request_enable,
|
||||
.gpio_set_direction = mvebu_pinmux_gpio_set_direction,
|
||||
.enable = mvebu_pinmux_enable,
|
||||
};
|
||||
|
||||
static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
|
||||
{
|
||||
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
return pctl->num_groups;
|
||||
}
|
||||
|
||||
static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
|
||||
unsigned gid)
|
||||
{
|
||||
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
return pctl->groups[gid].name;
|
||||
}
|
||||
|
||||
static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
|
||||
unsigned gid, const unsigned **pins,
|
||||
unsigned *num_pins)
|
||||
{
|
||||
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
*pins = pctl->groups[gid].pins;
|
||||
*num_pins = pctl->groups[gid].npins;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
|
||||
struct device_node *np,
|
||||
struct pinctrl_map **map,
|
||||
unsigned *num_maps)
|
||||
{
|
||||
struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
|
||||
struct property *prop;
|
||||
const char *function;
|
||||
const char *group;
|
||||
int ret, nmaps, n;
|
||||
|
||||
*map = NULL;
|
||||
*num_maps = 0;
|
||||
|
||||
ret = of_property_read_string(np, "marvell,function", &function);
|
||||
if (ret) {
|
||||
dev_err(pctl->dev,
|
||||
"missing marvell,function in node %s\n", np->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
nmaps = of_property_count_strings(np, "marvell,pins");
|
||||
if (nmaps < 0) {
|
||||
dev_err(pctl->dev,
|
||||
"missing marvell,pins in node %s\n", np->name);
|
||||
return 0;
|
||||
}
|
||||
|
||||
*map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
|
||||
if (map == NULL) {
|
||||
dev_err(pctl->dev,
|
||||
"cannot allocate pinctrl_map memory for %s\n",
|
||||
np->name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
n = 0;
|
||||
of_property_for_each_string(np, "marvell,pins", prop, group) {
|
||||
struct mvebu_pinctrl_group *grp =
|
||||
mvebu_pinctrl_find_group_by_name(pctl, group);
|
||||
|
||||
if (!grp) {
|
||||
dev_err(pctl->dev, "unknown pin %s", group);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
|
||||
dev_err(pctl->dev, "unsupported function %s on pin %s",
|
||||
function, group);
|
||||
continue;
|
||||
}
|
||||
|
||||
(*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
|
||||
(*map)[n].data.mux.group = group;
|
||||
(*map)[n].data.mux.function = function;
|
||||
n++;
|
||||
}
|
||||
|
||||
*num_maps = nmaps;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
struct pinctrl_map *map, unsigned num_maps)
|
||||
{
|
||||
kfree(map);
|
||||
}
|
||||
|
||||
static struct pinctrl_ops mvebu_pinctrl_ops = {
|
||||
.get_groups_count = mvebu_pinctrl_get_groups_count,
|
||||
.get_group_name = mvebu_pinctrl_get_group_name,
|
||||
.get_group_pins = mvebu_pinctrl_get_group_pins,
|
||||
.dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
|
||||
.dt_free_map = mvebu_pinctrl_dt_free_map,
|
||||
};
|
||||
|
||||
static int __devinit _add_function(struct mvebu_pinctrl_function *funcs,
|
||||
const char *name)
|
||||
{
|
||||
while (funcs->num_groups) {
|
||||
/* function already there */
|
||||
if (strcmp(funcs->name, name) == 0) {
|
||||
funcs->num_groups++;
|
||||
return -EEXIST;
|
||||
}
|
||||
funcs++;
|
||||
}
|
||||
funcs->name = name;
|
||||
funcs->num_groups = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __devinit mvebu_pinctrl_build_functions(struct platform_device *pdev,
|
||||
struct mvebu_pinctrl *pctl)
|
||||
{
|
||||
struct mvebu_pinctrl_function *funcs;
|
||||
int num = 0;
|
||||
int n, s;
|
||||
|
||||
/* we allocate functions for number of pins and hope
|
||||
* there are less unique functions than pins available */
|
||||
funcs = devm_kzalloc(&pdev->dev, pctl->desc.npins *
|
||||
sizeof(struct mvebu_pinctrl_function), GFP_KERNEL);
|
||||
if (!funcs)
|
||||
return -ENOMEM;
|
||||
|
||||
for (n = 0; n < pctl->num_groups; n++) {
|
||||
struct mvebu_pinctrl_group *grp = &pctl->groups[n];
|
||||
for (s = 0; s < grp->num_settings; s++) {
|
||||
/* skip unsupported settings on this variant */
|
||||
if (pctl->variant &&
|
||||
!(pctl->variant & grp->settings[s].variant))
|
||||
continue;
|
||||
|
||||
/* check for unique functions and count groups */
|
||||
if (_add_function(funcs, grp->settings[s].name))
|
||||
continue;
|
||||
|
||||
num++;
|
||||
}
|
||||
}
|
||||
|
||||
/* with the number of unique functions and it's groups known,
|
||||
reallocate functions and assign group names */
|
||||
funcs = krealloc(funcs, num * sizeof(struct mvebu_pinctrl_function),
|
||||
GFP_KERNEL);
|
||||
if (!funcs)
|
||||
return -ENOMEM;
|
||||
|
||||
pctl->num_functions = num;
|
||||
pctl->functions = funcs;
|
||||
|
||||
for (n = 0; n < pctl->num_groups; n++) {
|
||||
struct mvebu_pinctrl_group *grp = &pctl->groups[n];
|
||||
for (s = 0; s < grp->num_settings; s++) {
|
||||
struct mvebu_pinctrl_function *f;
|
||||
const char **groups;
|
||||
|
||||
/* skip unsupported settings on this variant */
|
||||
if (pctl->variant &&
|
||||
!(pctl->variant & grp->settings[s].variant))
|
||||
continue;
|
||||
|
||||
f = mvebu_pinctrl_find_function_by_name(pctl,
|
||||
grp->settings[s].name);
|
||||
|
||||
/* allocate group name array if not done already */
|
||||
if (!f->groups) {
|
||||
f->groups = devm_kzalloc(&pdev->dev,
|
||||
f->num_groups * sizeof(char *),
|
||||
GFP_KERNEL);
|
||||
if (!f->groups)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* find next free group name and assign current name */
|
||||
groups = f->groups;
|
||||
while (*groups)
|
||||
groups++;
|
||||
*groups = grp->name;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct mvebu_pinctrl *pctl;
|
||||
void __iomem *base;
|
||||
struct pinctrl_pin_desc *pdesc;
|
||||
unsigned gid, n, k;
|
||||
int ret;
|
||||
|
||||
if (!soc || !soc->controls || !soc->modes) {
|
||||
dev_err(&pdev->dev, "wrong pinctrl soc info\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
base = of_iomap(np, 0);
|
||||
if (!base) {
|
||||
dev_err(&pdev->dev, "unable to get base address\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
|
||||
GFP_KERNEL);
|
||||
if (!pctl) {
|
||||
dev_err(&pdev->dev, "unable to alloc driver\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
pctl->desc.name = dev_name(&pdev->dev);
|
||||
pctl->desc.owner = THIS_MODULE;
|
||||
pctl->desc.pctlops = &mvebu_pinctrl_ops;
|
||||
pctl->desc.pmxops = &mvebu_pinmux_ops;
|
||||
pctl->desc.confops = &mvebu_pinconf_ops;
|
||||
pctl->variant = soc->variant;
|
||||
pctl->base = base;
|
||||
pctl->dev = &pdev->dev;
|
||||
platform_set_drvdata(pdev, pctl);
|
||||
|
||||
/* count controls and create names for mvebu generic
|
||||
register controls; also does sanity checks */
|
||||
pctl->num_groups = 0;
|
||||
pctl->desc.npins = 0;
|
||||
for (n = 0; n < soc->ncontrols; n++) {
|
||||
struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
|
||||
char *names;
|
||||
|
||||
pctl->desc.npins += ctrl->npins;
|
||||
/* initial control pins */
|
||||
for (k = 0; k < ctrl->npins; k++)
|
||||
ctrl->pins[k] = ctrl->pid + k;
|
||||
|
||||
/* special soc specific control */
|
||||
if (ctrl->mpp_get || ctrl->mpp_set) {
|
||||
if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
|
||||
dev_err(&pdev->dev, "wrong soc control info\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
pctl->num_groups += 1;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* generic mvebu register control */
|
||||
names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
|
||||
if (!names) {
|
||||
dev_err(&pdev->dev, "failed to alloc mpp names\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
for (k = 0; k < ctrl->npins; k++)
|
||||
sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
|
||||
ctrl->name = names;
|
||||
pctl->num_groups += ctrl->npins;
|
||||
}
|
||||
|
||||
pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
|
||||
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
|
||||
if (!pdesc) {
|
||||
dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
for (n = 0; n < pctl->desc.npins; n++)
|
||||
pdesc[n].number = n;
|
||||
pctl->desc.pins = pdesc;
|
||||
|
||||
pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
|
||||
sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
|
||||
if (!pctl->groups) {
|
||||
dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* assign mpp controls to groups */
|
||||
gid = 0;
|
||||
for (n = 0; n < soc->ncontrols; n++) {
|
||||
struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
|
||||
pctl->groups[gid].gid = gid;
|
||||
pctl->groups[gid].ctrl = ctrl;
|
||||
pctl->groups[gid].name = ctrl->name;
|
||||
pctl->groups[gid].pins = ctrl->pins;
|
||||
pctl->groups[gid].npins = ctrl->npins;
|
||||
|
||||
/* generic mvebu register control maps to a number of groups */
|
||||
if (!ctrl->mpp_get && !ctrl->mpp_set) {
|
||||
pctl->groups[gid].npins = 1;
|
||||
|
||||
for (k = 1; k < ctrl->npins; k++) {
|
||||
gid++;
|
||||
pctl->groups[gid].gid = gid;
|
||||
pctl->groups[gid].ctrl = ctrl;
|
||||
pctl->groups[gid].name = &ctrl->name[8*k];
|
||||
pctl->groups[gid].pins = &ctrl->pins[k];
|
||||
pctl->groups[gid].npins = 1;
|
||||
}
|
||||
}
|
||||
gid++;
|
||||
}
|
||||
|
||||
/* assign mpp modes to groups */
|
||||
for (n = 0; n < soc->nmodes; n++) {
|
||||
struct mvebu_mpp_mode *mode = &soc->modes[n];
|
||||
struct mvebu_pinctrl_group *grp =
|
||||
mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
|
||||
unsigned num_settings;
|
||||
|
||||
if (!grp) {
|
||||
dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
|
||||
mode->pid);
|
||||
continue;
|
||||
}
|
||||
|
||||
for (num_settings = 0; ;) {
|
||||
struct mvebu_mpp_ctrl_setting *set =
|
||||
&mode->settings[num_settings];
|
||||
|
||||
if (!set->name)
|
||||
break;
|
||||
num_settings++;
|
||||
|
||||
/* skip unsupported settings for this variant */
|
||||
if (pctl->variant && !(pctl->variant & set->variant))
|
||||
continue;
|
||||
|
||||
/* find gpio/gpo/gpi settings */
|
||||
if (strcmp(set->name, "gpio") == 0)
|
||||
set->flags = MVEBU_SETTING_GPI |
|
||||
MVEBU_SETTING_GPO;
|
||||
else if (strcmp(set->name, "gpo") == 0)
|
||||
set->flags = MVEBU_SETTING_GPO;
|
||||
else if (strcmp(set->name, "gpi") == 0)
|
||||
set->flags = MVEBU_SETTING_GPI;
|
||||
}
|
||||
|
||||
grp->settings = mode->settings;
|
||||
grp->num_settings = num_settings;
|
||||
}
|
||||
|
||||
ret = mvebu_pinctrl_build_functions(pdev, pctl);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "unable to build functions\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
|
||||
if (!pctl->pctldev) {
|
||||
dev_err(&pdev->dev, "unable to register pinctrl driver\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "registered pinctrl driver\n");
|
||||
|
||||
/* register gpio ranges */
|
||||
for (n = 0; n < soc->ngpioranges; n++)
|
||||
pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
|
||||
pinctrl_unregister(pctl->pctldev);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/*
|
||||
* Marvell MVEBU pinctrl driver
|
||||
*
|
||||
* Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#ifndef __PINCTRL_MVEBU_H__
|
||||
#define __PINCTRL_MVEBU_H__
|
||||
|
||||
/**
|
||||
* struct mvebu_mpp_ctrl - describe a mpp control
|
||||
* @name: name of the control group
|
||||
* @pid: first pin id handled by this control
|
||||
* @npins: number of pins controlled by this control
|
||||
* @mpp_get: (optional) special function to get mpp setting
|
||||
* @mpp_set: (optional) special function to set mpp setting
|
||||
* @mpp_gpio_req: (optional) special function to request gpio
|
||||
* @mpp_gpio_dir: (optional) special function to set gpio direction
|
||||
*
|
||||
* A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
|
||||
* internal function, inside the SoC. Each muxable unit can be switched
|
||||
* between two or more different settings, e.g. assign mpp pin 13 to
|
||||
* uart1 or sata.
|
||||
*
|
||||
* If optional mpp_get/_set functions are set these are used to get/set
|
||||
* a specific mode. Otherwise it is assumed that the mpp control is based
|
||||
* on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
|
||||
* functions can be used to allow pin settings with varying gpio pins.
|
||||
*/
|
||||
struct mvebu_mpp_ctrl {
|
||||
const char *name;
|
||||
u8 pid;
|
||||
u8 npins;
|
||||
unsigned *pins;
|
||||
int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
|
||||
int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
|
||||
int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
|
||||
int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
|
||||
* @val: ctrl setting value
|
||||
* @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
|
||||
* @subname: (optional) additional ctrl setting name, e.g. rts, cts
|
||||
* @variant: (optional) variant identifier mask
|
||||
* @flags: (private) flags to store gpi/gpo/gpio capabilities
|
||||
*
|
||||
* A ctrl_setting describes a specific internal mux function that a mpp pin
|
||||
* can be switched to. The value (val) will be written in the corresponding
|
||||
* register for common mpp pin configuration registers on MVEBU. SoC specific
|
||||
* mpp_get/_set function may use val to distinguish between different settings.
|
||||
*
|
||||
* The name will be used to switch to this setting in DT description, e.g.
|
||||
* marvell,function = "uart2". subname is only for debugging purposes.
|
||||
*
|
||||
* If name is one of "gpi", "gpo", "gpio" gpio capabilities are
|
||||
* parsed during initialization and stored in flags.
|
||||
*
|
||||
* The variant can be used to combine different revisions of one SoC to a
|
||||
* common pinctrl driver. It is matched (AND) with variant of soc_info to
|
||||
* determine if a setting is available on the current SoC revision.
|
||||
*/
|
||||
struct mvebu_mpp_ctrl_setting {
|
||||
u8 val;
|
||||
const char *name;
|
||||
const char *subname;
|
||||
u8 variant;
|
||||
u8 flags;
|
||||
#define MVEBU_SETTING_GPO (1 << 0)
|
||||
#define MVEBU_SETTING_GPI (1 << 1)
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mvebu_mpp_mode - link ctrl and settings
|
||||
* @pid: first pin id handled by this mode
|
||||
* @settings: list of settings available for this mode
|
||||
*
|
||||
* A mode connects all available settings with the corresponding mpp_ctrl
|
||||
* given by pid.
|
||||
*/
|
||||
struct mvebu_mpp_mode {
|
||||
u8 pid;
|
||||
struct mvebu_mpp_ctrl_setting *settings;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
|
||||
* @variant: variant mask of soc_info
|
||||
* @controls: list of available mvebu_mpp_ctrls
|
||||
* @ncontrols: number of available mvebu_mpp_ctrls
|
||||
* @modes: list of available mvebu_mpp_modes
|
||||
* @nmodes: number of available mvebu_mpp_modes
|
||||
* @gpioranges: list of pinctrl_gpio_ranges
|
||||
* @ngpioranges: number of available pinctrl_gpio_ranges
|
||||
*
|
||||
* This struct describes all pinctrl related information for a specific SoC.
|
||||
* If variant is unequal 0 it will be matched (AND) with variant of each
|
||||
* setting and allows to distinguish between different revisions of one SoC.
|
||||
*/
|
||||
struct mvebu_pinctrl_soc_info {
|
||||
u8 variant;
|
||||
struct mvebu_mpp_ctrl *controls;
|
||||
int ncontrols;
|
||||
struct mvebu_mpp_mode *modes;
|
||||
int nmodes;
|
||||
struct pinctrl_gpio_range *gpioranges;
|
||||
int ngpioranges;
|
||||
};
|
||||
|
||||
#define MPP_REG_CTRL(_idl, _idh) \
|
||||
{ \
|
||||
.name = NULL, \
|
||||
.pid = _idl, \
|
||||
.npins = _idh - _idl + 1, \
|
||||
.pins = (unsigned[_idh - _idl + 1]) { }, \
|
||||
.mpp_get = NULL, \
|
||||
.mpp_set = NULL, \
|
||||
.mpp_gpio_req = NULL, \
|
||||
.mpp_gpio_dir = NULL, \
|
||||
}
|
||||
|
||||
#define MPP_FUNC_CTRL(_idl, _idh, _name, _func) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.pid = _idl, \
|
||||
.npins = _idh - _idl + 1, \
|
||||
.pins = (unsigned[_idh - _idl + 1]) { }, \
|
||||
.mpp_get = _func ## _get, \
|
||||
.mpp_set = _func ## _set, \
|
||||
.mpp_gpio_req = NULL, \
|
||||
.mpp_gpio_dir = NULL, \
|
||||
}
|
||||
|
||||
#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func) \
|
||||
{ \
|
||||
.name = _name, \
|
||||
.pid = _idl, \
|
||||
.npins = _idh - _idl + 1, \
|
||||
.pins = (unsigned[_idh - _idl + 1]) { }, \
|
||||
.mpp_get = _func ## _get, \
|
||||
.mpp_set = _func ## _set, \
|
||||
.mpp_gpio_req = _func ## _gpio_req, \
|
||||
.mpp_gpio_dir = _func ## _gpio_dir, \
|
||||
}
|
||||
|
||||
#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
|
||||
{ \
|
||||
.val = _val, \
|
||||
.name = _name, \
|
||||
.subname = _subname, \
|
||||
.variant = _mask, \
|
||||
.flags = 0, \
|
||||
}
|
||||
|
||||
#if defined(CONFIG_DEBUG_FS)
|
||||
#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
|
||||
_MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
|
||||
#else
|
||||
#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask) \
|
||||
_MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
|
||||
#endif
|
||||
|
||||
#define MPP_FUNCTION(_val, _name, _subname) \
|
||||
MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
|
||||
|
||||
#define MPP_MODE(_id, ...) \
|
||||
{ \
|
||||
.pid = _id, \
|
||||
.settings = (struct mvebu_mpp_ctrl_setting[]){ \
|
||||
__VA_ARGS__, { } }, \
|
||||
}
|
||||
|
||||
#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins) \
|
||||
{ \
|
||||
.name = "mvebu-gpio", \
|
||||
.id = _id, \
|
||||
.pin_base = _pinbase, \
|
||||
.base = _gpiobase, \
|
||||
.npins = _npins, \
|
||||
}
|
||||
|
||||
int mvebu_pinctrl_probe(struct platform_device *pdev);
|
||||
int mvebu_pinctrl_remove(struct platform_device *pdev);
|
||||
|
||||
#endif
|
||||
Reference in New Issue