ARM: socfpga: initial support for Altera's SOCFPGA platform
Adding core definitions for Altera's SOCFPGA ARM platform. Mininum support for Altera's SOCFPGA Cyclone 5 hardware. Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
parent
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10
MAINTAINERS
10
MAINTAINERS
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@ -1111,6 +1111,16 @@ S: Supported
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F: arch/arm/mach-shmobile/
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F: arch/arm/mach-shmobile/
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F: drivers/sh/
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F: drivers/sh/
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ARM/SOCFPGA ARCHITECTURE
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M: Dinh Nguyen <dinguyen@altera.com>
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S: Maintained
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F: arch/arm/mach-socfpga/
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ARM/SOCFPGA CLOCK FRAMEWORK SUPPORT
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M: Dinh Nguyen <dinguyen@altera.com>
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S: Maintained
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F: drivers/clk/socfpga/
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ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
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ARM/TECHNOLOGIC SYSTEMS TS7250 MACHINE SUPPORT
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M: Lennert Buytenhek <kernel@wantstofly.org>
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M: Lennert Buytenhek <kernel@wantstofly.org>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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@ -250,6 +250,25 @@ choice
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prompt "ARM system type"
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prompt "ARM system type"
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default ARCH_VERSATILE
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default ARCH_VERSATILE
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config ARCH_SOCFPGA
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bool "Altera SOCFPGA family"
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select ARCH_WANT_OPTIONAL_GPIOLIB
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select ARM_AMBA
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select ARM_GIC
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select CACHE_L2X0
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select CLKDEV_LOOKUP
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select COMMON_CLK
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select CPU_V7
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select DW_APB_TIMER
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select DW_APB_TIMER_OF
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select GENERIC_CLOCKEVENTS
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select GPIO_PL061 if GPIOLIB
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select HAVE_ARM_SCU
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select SPARSE_IRQ
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select USE_OF
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help
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This enables support for Altera SOCFPGA Cyclone V platform
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config ARCH_INTEGRATOR
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config ARCH_INTEGRATOR
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bool "ARM Ltd. Integrator family"
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bool "ARM Ltd. Integrator family"
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select ARM_AMBA
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select ARM_AMBA
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@ -187,6 +187,7 @@ machine-$(CONFIG_ARCH_VEXPRESS) := vexpress
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machine-$(CONFIG_ARCH_VT8500) := vt8500
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machine-$(CONFIG_ARCH_VT8500) := vt8500
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machine-$(CONFIG_ARCH_W90X900) := w90x900
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machine-$(CONFIG_ARCH_W90X900) := w90x900
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machine-$(CONFIG_FOOTBRIDGE) := footbridge
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machine-$(CONFIG_FOOTBRIDGE) := footbridge
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machine-$(CONFIG_ARCH_SOCFPGA) := socfpga
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machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
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machine-$(CONFIG_MACH_SPEAR1310) := spear13xx
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machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
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machine-$(CONFIG_MACH_SPEAR1340) := spear13xx
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machine-$(CONFIG_MACH_SPEAR300) := spear3xx
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machine-$(CONFIG_MACH_SPEAR300) := spear3xx
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@ -0,0 +1,147 @@
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/*
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* Copyright (C) 2012 Altera <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/include/ "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &gmac0;
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serial0 = &uart0;
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serial1 = &uart1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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device_type = "cpu";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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};
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intc: intc@fffed000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xfffed000 0x1000>,
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<0xfffec100 0x100>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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device_type = "soc";
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interrupt-parent = <&intc>;
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ranges;
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amba {
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compatible = "arm,amba-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@ffe01000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0xffe01000 0x1000>;
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interrupts = <0 180 4>;
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};
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};
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gmac0: stmmac@ff700000 {
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compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xff700000 0x2000>;
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interrupts = <0 115 4>;
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interrupt-names = "macirq";
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mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
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phy-mode = "gmii";
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};
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L2: l2-cache@fffef000 {
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compatible = "arm,pl310-cache";
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reg = <0xfffef000 0x1000>;
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interrupts = <0 38 0x04>;
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cache-unified;
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cache-level = <2>;
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};
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/* Local timer */
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timer@fffec600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfffec600 0x100>;
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interrupts = <1 13 0xf04>;
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};
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timer0: timer@ffc08000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 167 4>;
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clock-frequency = <200000000>;
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reg = <0xffc08000 0x1000>;
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};
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timer1: timer@ffc09000 {
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compatible = "snps,dw-apb-timer-sp";
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interrupts = <0 168 4>;
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clock-frequency = <200000000>;
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reg = <0xffc09000 0x1000>;
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};
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timer2: timer@ffd00000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 169 4>;
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clock-frequency = <200000000>;
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reg = <0xffd00000 0x1000>;
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};
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timer3: timer@ffd01000 {
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compatible = "snps,dw-apb-timer-osc";
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interrupts = <0 170 4>;
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clock-frequency = <200000000>;
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reg = <0xffd01000 0x1000>;
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};
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uart0: uart@ffc02000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc02000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 162 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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uart1: uart@ffc03000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xffc03000 0x1000>;
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clock-frequency = <7372800>;
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interrupts = <0 163 4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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};
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};
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@ -0,0 +1,34 @@
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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||||||
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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||||||
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/dts-v1/;
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/include/ "socfpga.dtsi"
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/ {
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model = "Altera SOCFPGA Cyclone V";
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compatible = "altr,socfpga-cyclone5";
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chosen {
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bootargs = "console=ttyS0,57600";
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};
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memory {
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name = "memory";
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device_type = "memory";
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reg = <0x0 0x10000000>; /* 256MB */
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};
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};
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@ -0,0 +1,83 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=14
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CONFIG_CGROUPS=y
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CONFIG_CPUSETS=y
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CONFIG_NAMESPACES=y
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CONFIG_EMBEDDED=y
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CONFIG_PROFILING=y
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CONFIG_OPROFILE=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_LBDAF is not set
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_MACH_SOCFPGA_CYCLONE5=y
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CONFIG_ARM_THUMBEE=y
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# CONFIG_CACHE_L2X0 is not set
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_VMSPLIT_2G=y
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CONFIG_NR_CPUS=2
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CONFIG_AEABI=y
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE=""
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CONFIG_VFP=y
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CONFIG_NEON=y
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CONFIG_NET=y
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CONFIG_PACKET=y
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CONFIG_UNIX=y
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||||||
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CONFIG_NET_KEY=y
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||||||
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CONFIG_NET_KEY_MIGRATE=y
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CONFIG_INET=y
|
||||||
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CONFIG_IP_MULTICAST=y
|
||||||
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CONFIG_IP_PNP=y
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CONFIG_IP_PNP_DHCP=y
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||||||
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CONFIG_IP_PNP_BOOTP=y
|
||||||
|
CONFIG_IP_PNP_RARP=y
|
||||||
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||||
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CONFIG_DEVTMPFS=y
|
||||||
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CONFIG_PROC_DEVICETREE=y
|
||||||
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CONFIG_BLK_DEV_RAM=y
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||||||
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CONFIG_BLK_DEV_RAM_COUNT=2
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CONFIG_BLK_DEV_RAM_SIZE=8192
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CONFIG_SCSI=y
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# CONFIG_SCSI_PROC_FS is not set
|
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CONFIG_BLK_DEV_SD=y
|
||||||
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# CONFIG_SCSI_LOWLEVEL is not set
|
||||||
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CONFIG_NETDEVICES=y
|
||||||
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CONFIG_STMMAC_ETH=y
|
||||||
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# CONFIG_STMMAC_PHY_ID_ZERO_WORKAROUND is not set
|
||||||
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CONFIG_INPUT_EVDEV=y
|
||||||
|
# CONFIG_SERIO_SERPORT is not set
|
||||||
|
CONFIG_SERIO_AMBAKMI=y
|
||||||
|
CONFIG_LEGACY_PTY_COUNT=16
|
||||||
|
CONFIG_SERIAL_8250=y
|
||||||
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CONFIG_SERIAL_8250_CONSOLE=y
|
||||||
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CONFIG_SERIAL_8250_NR_UARTS=2
|
||||||
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CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||||
|
CONFIG_SERIAL_8250_DW=y
|
||||||
|
# CONFIG_RTC_HCTOSYS is not set
|
||||||
|
CONFIG_EXT2_FS=y
|
||||||
|
CONFIG_EXT2_FS_XATTR=y
|
||||||
|
CONFIG_EXT2_FS_POSIX_ACL=y
|
||||||
|
# CONFIG_DNOTIFY is not set
|
||||||
|
# CONFIG_INOTIFY_USER is not set
|
||||||
|
CONFIG_VFAT_FS=y
|
||||||
|
CONFIG_NTFS_FS=y
|
||||||
|
CONFIG_NTFS_RW=y
|
||||||
|
CONFIG_TMPFS=y
|
||||||
|
CONFIG_JFFS2_FS=y
|
||||||
|
CONFIG_NLS_CODEPAGE_437=y
|
||||||
|
CONFIG_NLS_ISO8859_1=y
|
||||||
|
CONFIG_MAGIC_SYSRQ=y
|
||||||
|
CONFIG_DETECT_HUNG_TASK=y
|
||||||
|
# CONFIG_SCHED_DEBUG is not set
|
||||||
|
CONFIG_DEBUG_INFO=y
|
||||||
|
CONFIG_ENABLE_DEFAULT_TRACERS=y
|
||||||
|
CONFIG_DEBUG_USER=y
|
||||||
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CONFIG_XZ_DEC=y
|
|
@ -0,0 +1,5 @@
|
||||||
|
#
|
||||||
|
# Makefile for the linux kernel.
|
||||||
|
#
|
||||||
|
|
||||||
|
obj-y := socfpga.o
|
|
@ -0,0 +1 @@
|
||||||
|
zreladdr-y := 0x00008000
|
|
@ -0,0 +1,16 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 1994-1999 Russell King
|
||||||
|
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License version 2 as
|
||||||
|
* published by the Free Software Foundation.
|
||||||
|
*/
|
||||||
|
|
||||||
|
.macro addruart, rp, rv, tmp
|
||||||
|
mov \rp, #DEBUG_LL_UART_OFFSET
|
||||||
|
orr \rp, \rp, #0x00c00000
|
||||||
|
orr \rv, \rp, #0xfe000000 @ virtual base
|
||||||
|
orr \rp, \rp, #0xff000000 @ physical base
|
||||||
|
.endm
|
||||||
|
|
|
@ -0,0 +1,19 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2003 ARM Limited
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program; if not, write to the Free Software
|
||||||
|
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define CLOCK_TICK_RATE (50000000 / 16)
|
|
@ -0,0 +1,9 @@
|
||||||
|
#ifndef __MACH_UNCOMPRESS_H
|
||||||
|
#define __MACH_UNCOMPRESS_H
|
||||||
|
|
||||||
|
#define putc(c)
|
||||||
|
#define flush()
|
||||||
|
#define arch_decomp_setup()
|
||||||
|
#define arch_decomp_wdog()
|
||||||
|
|
||||||
|
#endif
|
|
@ -0,0 +1,62 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2012 Altera Corporation
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
#include <linux/dw_apb_timer.h>
|
||||||
|
#include <linux/of_irq.h>
|
||||||
|
#include <linux/of_platform.h>
|
||||||
|
|
||||||
|
#include <asm/hardware/cache-l2x0.h>
|
||||||
|
#include <asm/hardware/gic.h>
|
||||||
|
#include <asm/mach/arch.h>
|
||||||
|
|
||||||
|
extern void socfpga_init_clocks(void);
|
||||||
|
|
||||||
|
const static struct of_device_id irq_match[] = {
|
||||||
|
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
|
||||||
|
{}
|
||||||
|
};
|
||||||
|
|
||||||
|
static void __init gic_init_irq(void)
|
||||||
|
{
|
||||||
|
of_irq_init(irq_match);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void socfpga_cyclone5_restart(char mode, const char *cmd)
|
||||||
|
{
|
||||||
|
/* TODO: */
|
||||||
|
}
|
||||||
|
|
||||||
|
static void __init socfpga_cyclone5_init(void)
|
||||||
|
{
|
||||||
|
l2x0_of_init(0, ~0UL);
|
||||||
|
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
|
||||||
|
socfpga_init_clocks();
|
||||||
|
}
|
||||||
|
|
||||||
|
static const char *altera_dt_match[] = {
|
||||||
|
"altr,socfpga",
|
||||||
|
"altr,socfpga-cyclone5",
|
||||||
|
NULL
|
||||||
|
};
|
||||||
|
|
||||||
|
DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
|
||||||
|
.init_irq = gic_init_irq,
|
||||||
|
.handle_irq = gic_handle_irq,
|
||||||
|
.timer = &dw_apb_timer,
|
||||||
|
.init_machine = socfpga_cyclone5_init,
|
||||||
|
.restart = socfpga_cyclone5_restart,
|
||||||
|
.dt_compat = altera_dt_match,
|
||||||
|
MACHINE_END
|
|
@ -4,4 +4,5 @@ obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
|
||||||
clk-mux.o clk-divider.o clk-fixed-factor.o
|
clk-mux.o clk-divider.o clk-fixed-factor.o
|
||||||
# SoCs specific
|
# SoCs specific
|
||||||
obj-$(CONFIG_ARCH_MXS) += mxs/
|
obj-$(CONFIG_ARCH_MXS) += mxs/
|
||||||
|
obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
|
||||||
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
obj-$(CONFIG_PLAT_SPEAR) += spear/
|
||||||
|
|
|
@ -0,0 +1 @@
|
||||||
|
obj-y += clk.o
|
|
@ -0,0 +1,51 @@
|
||||||
|
/*
|
||||||
|
* Copyright (C) 2012 Altera Corporation <www.altera.com>
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; either version 2 of the License, or
|
||||||
|
* (at your option) any later version.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*
|
||||||
|
* You should have received a copy of the GNU General Public License
|
||||||
|
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||||
|
*/
|
||||||
|
#include <linux/clk.h>
|
||||||
|
#include <linux/clkdev.h>
|
||||||
|
#include <linux/clk-provider.h>
|
||||||
|
|
||||||
|
#define SOCFPGA_OSC1_CLK 10000000
|
||||||
|
#define SOCFPGA_MPU_CLK 800000000
|
||||||
|
#define SOCFPGA_MAIN_QSPI_CLK 432000000
|
||||||
|
#define SOCFPGA_MAIN_NAND_SDMMC_CLK 250000000
|
||||||
|
#define SOCFPGA_S2F_USR_CLK 125000000
|
||||||
|
|
||||||
|
void __init socfpga_init_clocks(void)
|
||||||
|
{
|
||||||
|
struct clk *clk;
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "osc1_clk", NULL, CLK_IS_ROOT, SOCFPGA_OSC1_CLK);
|
||||||
|
clk_register_clkdev(clk, "osc1_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "mpu_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK);
|
||||||
|
clk_register_clkdev(clk, "mpu_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "main_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
|
||||||
|
clk_register_clkdev(clk, "main_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "dbg_base_clk", NULL, CLK_IS_ROOT, SOCFPGA_MPU_CLK/2);
|
||||||
|
clk_register_clkdev(clk, "dbg_base_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "main_qspi_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_QSPI_CLK);
|
||||||
|
clk_register_clkdev(clk, "main_qspi_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "main_nand_sdmmc_clk", NULL, CLK_IS_ROOT, SOCFPGA_MAIN_NAND_SDMMC_CLK);
|
||||||
|
clk_register_clkdev(clk, "main_nand_sdmmc_clk", NULL);
|
||||||
|
|
||||||
|
clk = clk_register_fixed_rate(NULL, "s2f_usr_clk", NULL, CLK_IS_ROOT, SOCFPGA_S2F_USR_CLK);
|
||||||
|
clk_register_clkdev(clk, "s2f_usr_clk", NULL);
|
||||||
|
}
|
|
@ -53,4 +53,5 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
|
||||||
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
|
cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
|
||||||
void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
|
void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
|
||||||
|
|
||||||
|
extern struct sys_timer dw_apb_timer;
|
||||||
#endif /* __DW_APB_TIMER_H__ */
|
#endif /* __DW_APB_TIMER_H__ */
|
||||||
|
|
Reference in New Issue