CRIS: Update documentation
Change some broken links, remove obsolete information and add information about the CRISv32 architecture. Signed-off-by: Jesper Nilsson <jesper.nilsson@axis.com>
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Linux 2.4 on the CRIS architecture
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Linux on the CRIS architecture
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==================================
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==============================
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$Id: README,v 1.7 2001/04/19 12:38:32 bjornw Exp $
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This is a port of Linux 2.4 to Axis Communications ETRAX 100LX embedded
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This is a port of Linux to Axis Communications ETRAX 100LX,
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network CPU. For more information about CRIS and ETRAX please see further
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ETRAX FS and ARTPEC-3 embedded network CPUs.
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below.
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For more information about CRIS and ETRAX please see further below.
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In order to compile this you need a version of gcc with support for the
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In order to compile this you need a version of gcc with support for the
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ETRAX chip family. Please see this link for more information on how to
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ETRAX chip family. Please see this link for more information on how to
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download the compiler and other tools useful when building and booting
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download the compiler and other tools useful when building and booting
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software for the ETRAX platform:
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software for the ETRAX platform:
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http://developer.axis.com/doc/software/devboard_lx/install-howto.html
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http://developer.axis.com/wiki/doku.php?id=axis:install-howto-2_20
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<more specific information should come in this document later>
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What is CRIS ?
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What is CRIS ?
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--------------
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--------------
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CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU
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CRIS is an acronym for 'Code Reduced Instruction Set'. It is the CPU
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architecture in Axis Communication AB's range of embedded network CPU's,
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architecture in Axis Communication AB's range of embedded network CPU's,
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called ETRAX. The latest CPU is called ETRAX 100LX, where LX stands for
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called ETRAX.
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'Linux' because the chip was designed to be a good host for the Linux
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operating system.
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The ETRAX 100LX chip
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The ETRAX 100LX chip
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--------------------
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--------------------
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For reference, please see the press-release:
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For reference, please see the following link:
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http://www.axis.com/news/us/001101_etrax.htm
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http://www.axis.com/products/dev_etrax_100lx/index.htm
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The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
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The ETRAX 100LX is a 100 MIPS processor with 8kB cache, MMU, and a very broad
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range of built-in interfaces, all with modern scatter/gather DMA.
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range of built-in interfaces, all with modern scatter/gather DMA.
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Memory interfaces:
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Memory interfaces:
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@ -51,20 +47,28 @@ I/O interfaces:
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* SCSI
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* SCSI
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* two parallel-ports
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* two parallel-ports
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* two generic 8-bit ports
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* two generic 8-bit ports
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(not all interfaces are available at the same time due to chip pin
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(not all interfaces are available at the same time due to chip pin
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multiplexing)
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multiplexing)
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The previous version of the ETRAX, the ETRAX 100, sits in almost all of
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ETRAX 100LX is CRISv10 architecture.
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Axis shipping thin-servers like the Axis 2100 web camera or the ETRAX 100
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developer-board. It lacks an MMU so the Linux we run on that is a version
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of uClinux (Linux 2.0 without MM-support) ported to the CRIS architecture.
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The new Linux 2.4 port has full MM and needs a CPU with an MMU, so it will
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not run on the ETRAX 100.
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A version of the Axis developer-board with ETRAX 100LX (running Linux
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2.4) is now available. For more information please see developer.axis.com.
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The ETRAX FS and ARTPEC-3 chips
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-------------------------------
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The ETRAX FS is a 200MHz 32-bit RISC processor with on-chip 16kB
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I-cache and 16kB D-cache and with a wide range of device interfaces
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including multiple high speed serial ports and an integrated USB 1.1 PHY.
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The ARTPEC-3 is a variant of the ETRAX FS with additional IO-units
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used by the Axis Communications network cameras.
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See below link for more information:
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http://www.axis.com/products/dev_etrax_fs/index.htm
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ETRAX FS and ARTPEC-3 are both CRISv32 architectures.
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Bootlog
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Bootlog
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-------
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-------
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@ -182,10 +186,6 @@ SwapFree: 0 kB
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-rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd
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-rwxr-xr-x 1 342 100 16252 Jan 01 00:00 telnetd
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(All programs are statically linked to the libc at this point - we have not ported the
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shared libraries yet)
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