2008-01-27 10:39:16 +00:00
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/*
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2009-09-24 14:11:24 +00:00
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* Blackfin CPLB exception handling for when MPU in on
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2008-01-27 10:39:16 +00:00
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*
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2009-09-24 14:11:24 +00:00
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* Copyright 2008-2009 Analog Devices Inc.
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2008-01-27 10:39:16 +00:00
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*
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2009-09-24 14:11:24 +00:00
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* Licensed under the GPL-2 or later.
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2008-01-27 10:39:16 +00:00
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*/
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2009-09-24 14:11:24 +00:00
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2008-01-27 10:39:16 +00:00
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <asm/blackfin.h>
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2008-10-16 15:25:34 +00:00
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#include <asm/cacheflush.h>
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2009-08-07 01:20:58 +00:00
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#include <asm/cplb.h>
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2008-01-27 10:39:16 +00:00
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#include <asm/cplbinit.h>
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#include <asm/mmu_context.h>
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2009-01-07 15:14:38 +00:00
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/*
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* WARNING
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*
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* This file is compiled with certain -ffixed-reg options. We have to
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* make sure not to call any functions here that could clobber these
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* registers.
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*/
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2008-01-27 10:39:16 +00:00
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int page_mask_nelts;
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int page_mask_order;
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2008-11-18 09:48:22 +00:00
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unsigned long *current_rwx_mask[NR_CPUS];
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2008-01-27 10:39:16 +00:00
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2008-11-18 09:48:22 +00:00
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int nr_dcplb_miss[NR_CPUS], nr_icplb_miss[NR_CPUS];
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int nr_icplb_supv_miss[NR_CPUS], nr_dcplb_prot[NR_CPUS];
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int nr_cplb_flush[NR_CPUS];
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2008-01-27 10:39:16 +00:00
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2010-01-20 07:25:31 +00:00
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#ifdef CONFIG_EXCPT_IRQ_SYSC_L1
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#define MGR_ATTR __attribute__((l1_text))
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#else
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#define MGR_ATTR
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#endif
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2008-01-27 10:39:16 +00:00
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/*
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* Given the contents of the status register, return the index of the
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* CPLB that caused the fault.
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*/
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static inline int faulting_cplb_index(int status)
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{
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int signbits = __builtin_bfin_norm_fr1x32(status & 0xFFFF);
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return 30 - signbits;
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}
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/*
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* Given the contents of the status register and the DCPLB_DATA contents,
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* return true if a write access should be permitted.
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*/
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static inline int write_permitted(int status, unsigned long data)
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{
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if (status & FAULT_USERSUPV)
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return !!(data & CPLB_SUPV_WR);
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else
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return !!(data & CPLB_USER_WR);
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}
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/* Counters to implement round-robin replacement. */
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2008-11-18 09:48:22 +00:00
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static int icplb_rr_index[NR_CPUS], dcplb_rr_index[NR_CPUS];
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2008-01-27 10:39:16 +00:00
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/*
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* Find an ICPLB entry to be evicted and return its index.
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*/
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2010-01-20 07:25:31 +00:00
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MGR_ATTR static int evict_one_icplb(unsigned int cpu)
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2008-01-27 10:39:16 +00:00
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{
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int i;
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for (i = first_switched_icplb; i < MAX_CPLBS; i++)
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2008-11-18 09:48:22 +00:00
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if ((icplb_tbl[cpu][i].data & CPLB_VALID) == 0)
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2008-01-27 10:39:16 +00:00
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return i;
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2008-11-18 09:48:22 +00:00
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i = first_switched_icplb + icplb_rr_index[cpu];
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2008-01-27 10:39:16 +00:00
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_icplb;
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2008-11-18 09:48:22 +00:00
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icplb_rr_index[cpu] -= MAX_CPLBS - first_switched_icplb;
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2008-01-27 10:39:16 +00:00
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}
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2008-11-18 09:48:22 +00:00
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icplb_rr_index[cpu]++;
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2008-01-27 10:39:16 +00:00
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return i;
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}
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2010-01-20 07:25:31 +00:00
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MGR_ATTR static int evict_one_dcplb(unsigned int cpu)
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2008-01-27 10:39:16 +00:00
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{
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int i;
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for (i = first_switched_dcplb; i < MAX_CPLBS; i++)
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2008-11-18 09:48:22 +00:00
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if ((dcplb_tbl[cpu][i].data & CPLB_VALID) == 0)
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2008-01-27 10:39:16 +00:00
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return i;
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2008-11-18 09:48:22 +00:00
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i = first_switched_dcplb + dcplb_rr_index[cpu];
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2008-01-27 10:39:16 +00:00
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if (i >= MAX_CPLBS) {
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i -= MAX_CPLBS - first_switched_dcplb;
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2008-11-18 09:48:22 +00:00
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dcplb_rr_index[cpu] -= MAX_CPLBS - first_switched_dcplb;
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2008-01-27 10:39:16 +00:00
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}
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2008-11-18 09:48:22 +00:00
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dcplb_rr_index[cpu]++;
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2008-01-27 10:39:16 +00:00
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return i;
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}
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2010-01-20 07:25:31 +00:00
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MGR_ATTR static noinline int dcplb_miss(unsigned int cpu)
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2008-01-27 10:39:16 +00:00
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{
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unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
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int status = bfin_read_DCPLB_STATUS();
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unsigned long *mask;
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int idx;
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unsigned long d_data;
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2008-11-18 09:48:22 +00:00
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nr_dcplb_miss[cpu]++;
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2008-01-27 10:39:16 +00:00
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d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
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2009-06-16 09:48:33 +00:00
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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2009-06-10 06:26:26 +00:00
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if (bfin_addr_dcacheable(addr)) {
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2008-04-22 23:26:23 +00:00
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d_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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2009-06-16 09:48:33 +00:00
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# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
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2008-04-22 23:26:23 +00:00
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d_data |= CPLB_L1_AOW | CPLB_WT;
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2009-06-16 09:48:33 +00:00
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# endif
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2008-01-27 10:39:16 +00:00
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}
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2008-04-22 23:26:23 +00:00
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#endif
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2009-06-16 09:48:33 +00:00
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if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
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addr = L2_START;
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d_data = L2_DMEMORY;
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} else if (addr >= physical_mem_end) {
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2009-12-02 02:50:43 +00:00
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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2009-12-07 10:05:58 +00:00
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mask = current_rwx_mask[cpu];
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if (mask) {
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int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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if (mask[idx] & bit)
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d_data |= CPLB_USER_RD;
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}
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2008-04-23 21:44:32 +00:00
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} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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&& (status & (FAULT_RW | FAULT_USERSUPV)) == FAULT_USERSUPV) {
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addr &= ~(1 * 1024 * 1024 - 1);
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d_data &= ~PAGE_SIZE_4KB;
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2008-04-23 23:23:36 +00:00
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d_data |= PAGE_SIZE_1MB;
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2008-04-22 23:26:23 +00:00
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} else
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return CPLB_PROT_VIOL;
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2008-04-23 18:58:26 +00:00
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} else if (addr >= _ramend) {
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2009-12-09 07:01:50 +00:00
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d_data |= CPLB_USER_RD | CPLB_USER_WR;
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if (reserved_mem_dcache_on)
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d_data |= CPLB_L1_CHBL;
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2008-04-22 23:26:23 +00:00
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} else {
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2008-11-18 09:48:22 +00:00
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mask = current_rwx_mask[cpu];
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2008-04-22 23:26:23 +00:00
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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2008-11-18 09:48:22 +00:00
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int idx = page >> 5;
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2008-04-22 23:26:23 +00:00
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int bit = 1 << (page & 31);
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2008-11-18 09:48:22 +00:00
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if (mask[idx] & bit)
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2008-04-22 23:26:23 +00:00
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d_data |= CPLB_USER_RD;
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2008-01-27 10:39:16 +00:00
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2008-04-22 23:26:23 +00:00
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mask += page_mask_nelts;
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2008-11-18 09:48:22 +00:00
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if (mask[idx] & bit)
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2008-04-22 23:26:23 +00:00
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d_data |= CPLB_USER_WR;
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}
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}
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2008-11-18 09:48:22 +00:00
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idx = evict_one_dcplb(cpu);
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2008-01-27 10:39:16 +00:00
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addr &= PAGE_MASK;
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2008-11-18 09:48:22 +00:00
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dcplb_tbl[cpu][idx].addr = addr;
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dcplb_tbl[cpu][idx].data = d_data;
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2008-01-27 10:39:16 +00:00
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2009-08-07 01:20:58 +00:00
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_disable_dcplb();
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2008-01-27 10:39:16 +00:00
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bfin_write32(DCPLB_DATA0 + idx * 4, d_data);
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bfin_write32(DCPLB_ADDR0 + idx * 4, addr);
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2009-08-07 01:20:58 +00:00
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_enable_dcplb();
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2008-01-27 10:39:16 +00:00
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return 0;
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}
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2010-01-20 07:25:31 +00:00
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MGR_ATTR static noinline int icplb_miss(unsigned int cpu)
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2008-01-27 10:39:16 +00:00
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{
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unsigned long addr = bfin_read_ICPLB_FAULT_ADDR();
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int status = bfin_read_ICPLB_STATUS();
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int idx;
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unsigned long i_data;
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2008-11-18 09:48:22 +00:00
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nr_icplb_miss[cpu]++;
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2008-01-27 10:39:16 +00:00
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2008-04-23 18:58:26 +00:00
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/* If inside the uncached DMA region, fault. */
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if (addr >= _ramend - DMA_UNCACHED_REGION && addr < _ramend)
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2008-01-27 10:39:16 +00:00
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return CPLB_PROT_VIOL;
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2008-04-23 18:58:26 +00:00
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if (status & FAULT_USERSUPV)
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2008-11-18 09:48:22 +00:00
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nr_icplb_supv_miss[cpu]++;
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2008-04-23 18:58:26 +00:00
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2008-01-27 10:39:16 +00:00
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/*
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* First, try to find a CPLB that matches this address. If we
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* find one, then the fact that we're in the miss handler means
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* that the instruction crosses a page boundary.
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*/
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for (idx = first_switched_icplb; idx < MAX_CPLBS; idx++) {
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2008-11-18 09:48:22 +00:00
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if (icplb_tbl[cpu][idx].data & CPLB_VALID) {
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unsigned long this_addr = icplb_tbl[cpu][idx].addr;
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2008-01-27 10:39:16 +00:00
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if (this_addr <= addr && this_addr + PAGE_SIZE > addr) {
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addr += PAGE_SIZE;
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break;
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}
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}
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}
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i_data = CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4KB;
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2009-06-16 09:48:33 +00:00
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#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
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2008-01-27 10:39:16 +00:00
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/*
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2008-04-23 18:58:26 +00:00
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* Normal RAM, and possibly the reserved memory area, are
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* cacheable.
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2008-01-27 10:39:16 +00:00
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*/
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2008-04-23 18:58:26 +00:00
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if (addr < _ramend ||
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(addr < physical_mem_end && reserved_mem_icache_on))
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i_data |= CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#endif
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2008-01-27 10:39:16 +00:00
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2009-06-16 09:48:33 +00:00
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if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
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addr = L2_START;
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i_data = L2_IMEMORY;
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} else if (addr >= physical_mem_end) {
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2009-12-02 02:50:43 +00:00
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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2009-12-07 10:05:58 +00:00
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if (!(status & FAULT_USERSUPV)) {
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unsigned long *mask = current_rwx_mask[cpu];
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if (mask) {
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int page = (addr - (ASYNC_BANK0_BASE - _ramend)) >> PAGE_SHIFT;
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int idx = page >> 5;
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int bit = 1 << (page & 31);
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mask += 2 * page_mask_nelts;
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if (mask[idx] & bit)
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i_data |= CPLB_USER_RD;
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}
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}
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2009-12-02 02:50:43 +00:00
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} else if (addr >= BOOT_ROM_START && addr < BOOT_ROM_START + BOOT_ROM_LENGTH
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2008-04-23 23:23:36 +00:00
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&& (status & FAULT_USERSUPV)) {
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addr &= ~(1 * 1024 * 1024 - 1);
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i_data &= ~PAGE_SIZE_4KB;
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i_data |= PAGE_SIZE_1MB;
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} else
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return CPLB_PROT_VIOL;
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2008-04-23 18:58:26 +00:00
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} else if (addr >= _ramend) {
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i_data |= CPLB_USER_RD;
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2009-12-09 07:01:50 +00:00
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if (reserved_mem_icache_on)
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i_data |= CPLB_L1_CHBL;
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2008-04-23 18:58:26 +00:00
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} else {
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/*
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* Two cases to distinguish - a supervisor access must
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* necessarily be for a module page; we grant it
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* unconditionally (could do better here in the future).
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* Otherwise, check the x bitmap of the current process.
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*/
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if (!(status & FAULT_USERSUPV)) {
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2008-11-18 09:48:22 +00:00
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unsigned long *mask = current_rwx_mask[cpu];
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2008-04-23 18:58:26 +00:00
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if (mask) {
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int page = addr >> PAGE_SHIFT;
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2008-11-18 09:48:22 +00:00
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int idx = page >> 5;
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2008-04-23 18:58:26 +00:00
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int bit = 1 << (page & 31);
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mask += 2 * page_mask_nelts;
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2008-11-18 09:48:22 +00:00
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if (mask[idx] & bit)
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2008-04-23 18:58:26 +00:00
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i_data |= CPLB_USER_RD;
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}
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2008-01-27 10:39:16 +00:00
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}
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}
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2008-11-18 09:48:22 +00:00
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idx = evict_one_icplb(cpu);
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2008-01-27 10:39:16 +00:00
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addr &= PAGE_MASK;
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2008-11-18 09:48:22 +00:00
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icplb_tbl[cpu][idx].addr = addr;
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icplb_tbl[cpu][idx].data = i_data;
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2008-01-27 10:39:16 +00:00
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2009-08-07 01:20:58 +00:00
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_disable_icplb();
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2008-01-27 10:39:16 +00:00
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bfin_write32(ICPLB_DATA0 + idx * 4, i_data);
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bfin_write32(ICPLB_ADDR0 + idx * 4, addr);
|
2009-08-07 01:20:58 +00:00
|
|
|
_enable_icplb();
|
2008-01-27 10:39:16 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-01-20 07:25:31 +00:00
|
|
|
MGR_ATTR static noinline int dcplb_protection_fault(unsigned int cpu)
|
2008-01-27 10:39:16 +00:00
|
|
|
{
|
|
|
|
int status = bfin_read_DCPLB_STATUS();
|
|
|
|
|
2008-11-18 09:48:22 +00:00
|
|
|
nr_dcplb_prot[cpu]++;
|
2008-01-27 10:39:16 +00:00
|
|
|
|
|
|
|
if (status & FAULT_RW) {
|
|
|
|
int idx = faulting_cplb_index(status);
|
2008-11-18 09:48:22 +00:00
|
|
|
unsigned long data = dcplb_tbl[cpu][idx].data;
|
2008-01-27 10:39:16 +00:00
|
|
|
if (!(data & CPLB_WT) && !(data & CPLB_DIRTY) &&
|
|
|
|
write_permitted(status, data)) {
|
|
|
|
data |= CPLB_DIRTY;
|
2008-11-18 09:48:22 +00:00
|
|
|
dcplb_tbl[cpu][idx].data = data;
|
2008-01-27 10:39:16 +00:00
|
|
|
bfin_write32(DCPLB_DATA0 + idx * 4, data);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return CPLB_PROT_VIOL;
|
|
|
|
}
|
|
|
|
|
2010-01-20 07:25:31 +00:00
|
|
|
MGR_ATTR int cplb_hdr(int seqstat, struct pt_regs *regs)
|
2008-01-27 10:39:16 +00:00
|
|
|
{
|
|
|
|
int cause = seqstat & 0x3f;
|
2009-08-20 04:17:47 +00:00
|
|
|
unsigned int cpu = raw_smp_processor_id();
|
2008-01-27 10:39:16 +00:00
|
|
|
switch (cause) {
|
|
|
|
case 0x23:
|
2008-11-18 09:48:22 +00:00
|
|
|
return dcplb_protection_fault(cpu);
|
2008-01-27 10:39:16 +00:00
|
|
|
case 0x2C:
|
2008-11-18 09:48:22 +00:00
|
|
|
return icplb_miss(cpu);
|
2008-01-27 10:39:16 +00:00
|
|
|
case 0x26:
|
2008-11-18 09:48:22 +00:00
|
|
|
return dcplb_miss(cpu);
|
2008-01-27 10:39:16 +00:00
|
|
|
default:
|
2008-04-22 23:26:23 +00:00
|
|
|
return 1;
|
2008-01-27 10:39:16 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-11-18 09:48:22 +00:00
|
|
|
void flush_switched_cplbs(unsigned int cpu)
|
2008-01-27 10:39:16 +00:00
|
|
|
{
|
|
|
|
int i;
|
2008-10-07 08:27:01 +00:00
|
|
|
unsigned long flags;
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2008-11-18 09:48:22 +00:00
|
|
|
nr_cplb_flush[cpu]++;
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2010-10-07 13:08:52 +00:00
|
|
|
flags = hard_local_irq_save();
|
2009-08-07 01:20:58 +00:00
|
|
|
_disable_icplb();
|
2008-01-27 10:39:16 +00:00
|
|
|
for (i = first_switched_icplb; i < MAX_CPLBS; i++) {
|
2008-11-18 09:48:22 +00:00
|
|
|
icplb_tbl[cpu][i].data = 0;
|
2008-01-27 10:39:16 +00:00
|
|
|
bfin_write32(ICPLB_DATA0 + i * 4, 0);
|
|
|
|
}
|
2009-08-07 01:20:58 +00:00
|
|
|
_enable_icplb();
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2009-08-07 01:20:58 +00:00
|
|
|
_disable_dcplb();
|
2008-04-23 18:56:36 +00:00
|
|
|
for (i = first_switched_dcplb; i < MAX_CPLBS; i++) {
|
2008-11-18 09:48:22 +00:00
|
|
|
dcplb_tbl[cpu][i].data = 0;
|
2008-01-27 10:39:16 +00:00
|
|
|
bfin_write32(DCPLB_DATA0 + i * 4, 0);
|
|
|
|
}
|
2009-08-07 01:20:58 +00:00
|
|
|
_enable_dcplb();
|
2010-10-07 13:08:52 +00:00
|
|
|
hard_local_irq_restore(flags);
|
2008-10-07 08:27:01 +00:00
|
|
|
|
2008-01-27 10:39:16 +00:00
|
|
|
}
|
|
|
|
|
2008-11-18 09:48:22 +00:00
|
|
|
void set_mask_dcplbs(unsigned long *masks, unsigned int cpu)
|
2008-01-27 10:39:16 +00:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
unsigned long addr = (unsigned long)masks;
|
|
|
|
unsigned long d_data;
|
2008-10-07 08:27:01 +00:00
|
|
|
unsigned long flags;
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2008-10-07 08:27:01 +00:00
|
|
|
if (!masks) {
|
2008-11-18 09:48:22 +00:00
|
|
|
current_rwx_mask[cpu] = masks;
|
2008-01-27 10:39:16 +00:00
|
|
|
return;
|
2008-10-07 08:27:01 +00:00
|
|
|
}
|
|
|
|
|
2010-10-07 13:08:52 +00:00
|
|
|
flags = hard_local_irq_save();
|
2008-11-18 09:48:22 +00:00
|
|
|
current_rwx_mask[cpu] = masks;
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2009-06-16 09:48:33 +00:00
|
|
|
if (L2_LENGTH && addr >= L2_START && addr < L2_START + L2_LENGTH) {
|
|
|
|
addr = L2_START;
|
|
|
|
d_data = L2_DMEMORY;
|
|
|
|
} else {
|
|
|
|
d_data = CPLB_SUPV_WR | CPLB_VALID | CPLB_DIRTY | PAGE_SIZE_4KB;
|
|
|
|
#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
|
|
|
|
d_data |= CPLB_L1_CHBL;
|
|
|
|
# ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
|
|
|
|
d_data |= CPLB_L1_AOW | CPLB_WT;
|
|
|
|
# endif
|
2008-01-27 10:39:16 +00:00
|
|
|
#endif
|
2009-06-16 09:48:33 +00:00
|
|
|
}
|
2008-01-27 10:39:16 +00:00
|
|
|
|
2009-08-07 01:20:58 +00:00
|
|
|
_disable_dcplb();
|
2008-01-27 10:39:16 +00:00
|
|
|
for (i = first_mask_dcplb; i < first_switched_dcplb; i++) {
|
2008-11-18 09:48:22 +00:00
|
|
|
dcplb_tbl[cpu][i].addr = addr;
|
|
|
|
dcplb_tbl[cpu][i].data = d_data;
|
2008-01-27 10:39:16 +00:00
|
|
|
bfin_write32(DCPLB_DATA0 + i * 4, d_data);
|
|
|
|
bfin_write32(DCPLB_ADDR0 + i * 4, addr);
|
|
|
|
addr += PAGE_SIZE;
|
|
|
|
}
|
2009-08-07 01:20:58 +00:00
|
|
|
_enable_dcplb();
|
2010-10-07 13:08:52 +00:00
|
|
|
hard_local_irq_restore(flags);
|
2008-01-27 10:39:16 +00:00
|
|
|
}
|