304 lines
12 KiB
Plaintext
304 lines
12 KiB
Plaintext
[[dev_USRP1_inband_signaling_usb]]
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==== USRP1 in-band USB protocol
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This section specifies the format of USB packets used for in-band data
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transmission and signaling on the USRP1. All packets are 512-byte long, and are
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transferred using USB "bulk" transfers.
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IN packets are sent towards the host. OUT packets are sent away from the host.
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The layout is 32-bits wide. All data is transmitted in little-endian format
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across the USB.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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|O|U|D|S|E| RSSI | Chan | mbz | Tag | Payload Len |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Timestamp |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| |
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+ +
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| Payload |
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. .
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. .
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. .
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+ +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| ... | .
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+-+-+-+-+-+-+-+ .
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. .
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. Padding .
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. .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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mbz: Must be Zero::
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These bits must be zero in both IN and OUT packets.
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O: Overrun Flag::
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Set in an IN packet if an overrun condition was detected. Must be zero in OUT
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packets. Overrun occurs when the FPGA has data to transmit to the host and there
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is no buffer space available. This generally indicates a problem on the host.
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Either it is not keeping up, or it has configured the FPGA to transmit data at a
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higher rate than the transport (USB) can support.
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U: Underrun Flag::
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Set in an IN packet if an underrun condition was detected. Must be zero in OUT
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packets. Underrun occurs when the FPGA runs out of samples, and it's not between
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bursts. See the "End of Burst flag" below.
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D: Dropped Packet Flag::
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Set in an IN packet if the FPGA discarded an OUT packet because its timestamp
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had already passed.
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S: Start of Burst Flag::
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Set in an OUT packet if the data is the first segment of what is logically a
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continuous burst of data. Must be zero in IN packets.
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E: End of Burst Flag::
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Set in an OUT packet if the data is the last segment of what is logically a
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continuous burst of data. Must be zero in IN packets. Underruns are not
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reported when the FPGA runs out of samples between bursts.
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RSSI: 6-bit Received Strength Signal Indicator::
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Must be zero in OUT packets. In IN packets, indicates RSSI as reported by front
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end. FIXME The format and interpretation are to be determined.
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Chan: 5-bit logical channel number::
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Channel number 0x1f is reserved for control information. See "Control Channel"
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below. Other channels are "data channels". Each data channel is logically
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independent of the others. A data channel payload field contains a sequence of
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homogeneous samples. The format of the samples is determined by the
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configuration associated with the given channel. It is often the case that the
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payload field contains 32-bit complex samples, each containing 16-bit real and
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imaginary components.
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Tag::
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4-bit tag for matching IN packets with OUT packets.
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//FIXME, write more...
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Payload Len::
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9-bit field that specifies the length of the payload field in bytes. Must be in
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the range 0 to 504 inclusive.
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Timestamp: 32-bit timestamp::
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On IN packets, the timestamp indicates the time at which the first sample of the
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packet was produced by the A/D converter(s) for that channel. On OUT packets,
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the timestamp specifies the time at which the first sample in the packet should
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go out the D/A converter(s) for that channel. If a packet reaches the head of
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the transmit queue, and the current time is later than the timestamp, an error
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is assumed to have occurred and the packet is discarded. As a special case, the
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timestamp 0xffffffff is interpreted as "Now".
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The time base is a free running 32-bit counter that is incremented by the A/D
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sample-clock.
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Payload::
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Variable length field Length is specified by the Payload Len field.
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Padding::
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This field is 504 - Payload Len bytes long, and its content is unspecified.
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This field pads the packet out to a constant 512 bytes.
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===== "Data Channel" payload format
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If `Chan != 0x1f`, the packet is a "data packet" and the payload is a sequence of
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homogeneous samples. The format of the samples is determined by the
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configuration associated with the given channel. It is often the case that the
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payload field contains 32-bit complex samples, each containing 16-bit real and
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imaginary components.
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===== "Control Channel" payload format
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If `Chan == 0x1f`, the packet is a "control packet". The control channel payload
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consists of a sequence of 0 or more sub-packets.
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Each sub-packet starts on a 32-bit boundary, and consists of an 8-bit Opcode
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field, an 8-bit Length field, Length bytes of arguments, and 0, 1, 2 or 3 bytes
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of padding to align the tail of the sub-packet to a 32-bit boundary.
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Control channel packets shall be processed at the head of the queue, and shall
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observe the timestamp semantics described above.
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===== General sub-packet format
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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| Opcode | Length | <length bytes> ... |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-//-+-+-+-+-+-+-+-+
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----
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===== Specific sub-packet formats
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RID: 6-bit Request-ID::
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Copied from request sub-packet into corresponding reply sub-packet. RID allows
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the host to match requests and replies.
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Reg Number::
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10-bit Register Number.
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Ping Fixed Length::
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* Opcode: OP_PING_FIXED
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Ping Fixed Length Reply::
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* Opcode: OP_PING_FIXED_REPLY
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Ping Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Write Register::
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* Opcode: OP_WRITE_REG
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Write Register Masked::
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Only the register bits that correspond to 1's in the mask are written
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with the new value. `REG[Num] = (REG[Num] & ~Mask) | (Value & Mask)`
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* Opcode: OP_WRITE_REG_MASKED
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 10 | mbz | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Mask Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Read Register::
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* Opcode: OP_READ_REG
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Read Register Reply::
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* Opcode: OP_READ_REG_REPLY
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 6 | RID | Reg Number |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Register Value |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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I2C Write::
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* Opcode: OP_I2C_WRITE
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* I2C Addr: 7-bit I2C address
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* Data: The bytes to write to the I2C bus
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* Length: Length of Data + 2
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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I2C Read::
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* Opcode: OP_I2C_READ
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* I2C Addr: 7-bit I2C address
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* Nbytes: Number of bytes to read from I2C bus
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 3 | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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I2C Read Reply::
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* Opcode: OP_I2C_READ_REPLY
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* I2C Addr: 7-bit I2C address
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* Data: Length - 2 bytes of data read from I2C bus.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz | I2C Addr |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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SPI Write::
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* Opcode: OP_SPI_WRITE
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* Enables: Which SPI enables to assert (mask)
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* Format: Specifies format of SPI data and Opt Header Bytes
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* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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* Data: The bytes to write to the SPI bus
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* Length: Length of Data + 6
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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SPI Read::
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* Opcode: OP_SPI_READ
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* Enables: Which SPI enables to assert (mask)
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* Format: Specifies format of SPI data and Opt Header Bytes
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* Opt Header Bytes: 2-byte field containing optional Tx bytes; see Format
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* Nbytes: Number of bytes to read from SPI bus.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 7 | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Enables | Format | Opt Header Bytes |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Nbytes | unspecified padding |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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SPI Read Reply::
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* Opcode: OP_SPI_READ_REPLY
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* Data: Length - 2 bytes of data read from SPI bus.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | Length | RID | mbz |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Data ... .
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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Delay::
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* Opcode: OP_DELAY
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* Ticks: 16-bit unsigned delay count
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* Delay Ticks clock ticks before executing next operation.
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----
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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| Opcode | 2 | Ticks |
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+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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----
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