Currently we find SSE3 and SSE4.1 code mixed togehter along with
generic code in one file. This introduces the risk that the
compiler exidantly mixes SSE4.1 instructions into an SSE3, or
even worse into a generic code path.
This commit splits the SSE3 and SSE4.1 code into separate files
and compiles them with the matching target options.
Change-Id: I846e190e92f1258cd412d1b2d79b539e204e04b3
Currently the build environment checks which extension the current
CPU supports and picks the compiler flags accordingly.
If the build is happening on a machine that does not support the
extensions we need (SSE3, SSE4.1), the binary will lack those
extensions, even if its intended to be used on a more powerful
machine that would support the extensions.
This commit removes the CPU tests from the build process.
Change-Id: Ic913aa13c23c348ae62e78c9dfd6ed8b0a62798c
This large patch replaced the convolve() call with an SSE vector
enabled version. The lower C and SSE intrinsic based code operates
on fixed and aligned vectors for the filter taps. The storage format
of interleaved I/Q for both complex and real vectors is maintained.
SSE filter tap values must:
1. Start 16-byte aligned
2. Number with a multiple of 4 between 4 and 20 for real taps
3. Number with a multiple of 4 for complex taps
Non-compliant values will fall back to non-SSE usage. Fixed length
iterators mean that head and tail cases may require reallocation of
the input vector, which is automatically handled by the upper C++
interface.
Other calls are affected by these changes and adjusted or rewritten
accordingly. The underlying algorithms, however, are unchanged.
generateGSMPulse()
analyzeTrafficBurst()
detectRACHBurst()
Intel SSE configuration is automatically detected and configured at
build time with Autoconf macros.
Signed-off-by: Thomas Tsou <tom@tsou.cc>
Philipp Maier
Thomas Tsou