Transceiver: Support TRXD v1
Related: OS#4006 Change-Id: I53db2678458a7377c87875b58b58b76a1b900517
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@ -618,6 +618,10 @@ bool Transceiver::pullRadioVector(size_t chan, struct trx_ul_burst_ind *bi)
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bi->toa = 0.0;
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bi->noise = 0.0;
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bi->idle = false;
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bi->modulation = MODULATION_GMSK;
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bi->tss = 0; /* TODO: we only support tss 0 right now */
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bi->tsc = 0;
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bi->ci = 0.0;
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/* Select the diversity channel with highest energy */
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for (size_t i = 0; i < radio_burst->chans(); i++) {
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@ -665,13 +669,18 @@ bool Transceiver::pullRadioVector(size_t chan, struct trx_ul_burst_ind *bi)
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type = (CorrType) rc;
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bi->toa = ebp.toa;
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bi->tsc = ebp.tsc;
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bi->ci = ebp.ci;
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rxBurst = demodAnyBurst(*burst, mSPSRx, ebp.amp, ebp.toa, type);
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/* EDGE demodulator returns 444 (gSlotLen * 3) bits */
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if (rxBurst->size() == EDGE_BURST_NBITS)
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if (rxBurst->size() == EDGE_BURST_NBITS) {
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bi->modulation = MODULATION_8PSK;
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bi->nbits = EDGE_BURST_NBITS;
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else /* size() here is actually gSlotLen + 8, due to guard periods */
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} else { /* size() here is actually gSlotLen + 8, due to guard periods */
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bi->modulation = MODULATION_GMSK;
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bi->nbits = gSlotLen;
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}
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// Convert -1..+1 soft bits to 0..1 soft bits
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vectorSlicer(bi->rx_burst, rxBurst->begin(), bi->nbits);
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@ -980,6 +989,7 @@ void Transceiver::logRxBurst(size_t chan, const struct trx_ul_burst_ind *bi)
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<< " noise: " << std::setw(5) << std::setprecision(1) << (bi->noise - rssiOffset)
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<< "dBFS/" << std::setw(6) << -bi->noise << "dBm"
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<< " TOA: " << std::setw(5) << std::setprecision(2) << bi->toa
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<< " C/I: " << std::setw(5) << std::setprecision(2) << bi->ci << "dB"
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<< " bits: " << os;
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}
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@ -996,6 +1006,9 @@ void Transceiver::driveReceiveFIFO(size_t chan)
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case 0:
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trxd_send_burst_ind_v0(chan, mDataSockets[chan], &bi);
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break;
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case 1:
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trxd_send_burst_ind_v1(chan, mDataSockets[chan], &bi);
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break;
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default:
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OSMO_ASSERT(false);
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}
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@ -43,6 +43,21 @@ static void trxd_fill_v0_specific(struct trxd_hdr_v0_specific *v0, const struct
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osmo_store16be(toa_int, &v0->toa);
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}
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static void trxd_fill_v1_specific(struct trxd_hdr_v1_specific *v1, const struct trx_ul_burst_ind *bi)
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{
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int16_t ci_int_cB;
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/* deciBels->centiBels, round to closest integer */
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ci_int_cB = (int16_t)((bi->ci * 10) + 0.5);
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v1->idle = !!bi->idle;
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v1->modulation = (bi->modulation == MODULATION_GMSK) ?
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TRXD_MODULATION_GMSK(bi->tss) :
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TRXD_MODULATION_8PSK(bi->tss);
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v1->tsc = bi->tsc;
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osmo_store16be(ci_int_cB, &v1->ci);
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}
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static void trxd_fill_burst_normalized255(uint8_t* soft_bits, const struct trx_ul_burst_ind *bi)
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{
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unsigned i;
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@ -75,3 +90,28 @@ bool trxd_send_burst_ind_v0(size_t chan, int fd, const struct trx_ul_burst_ind *
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}
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return true;
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}
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bool trxd_send_burst_ind_v1(size_t chan, int fd, const struct trx_ul_burst_ind *bi) {
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int rc;
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size_t buf_len;
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buf_len = sizeof(struct trxd_hdr_v1);
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if (!bi->idle)
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buf_len += bi->nbits;
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char buf[buf_len];
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struct trxd_hdr_v1* pkt = (struct trxd_hdr_v1*)buf;
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trxd_fill_common(&pkt->common, bi, 1);
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trxd_fill_v0_specific(&pkt->v0, bi);
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trxd_fill_v1_specific(&pkt->v1, bi);
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if (!bi->idle)
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trxd_fill_burst_normalized255(&pkt->soft_bits[0], bi);
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rc = write(fd, buf, buf_len);
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if (rc <= 0) {
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CLOGCHAN(chan, DMAIN, LOGL_NOTICE, "mDataSockets write(%d) failed: %d\n", fd, rc);
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return false;
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}
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return true;
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}
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@ -11,6 +11,16 @@
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#define MAX_RX_BURST_BUF_SIZE 444 /* 444 = EDGE_BURST_NBITS */
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enum Modulation {
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MODULATION_GMSK,
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MODULATION_8PSK,
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/* Not supported yet:
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MODULATION_AQPSK,
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MODULATION_16QAM,
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MODULATION_32QAM
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*/
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};
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struct trx_ul_burst_ind {
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float rx_burst[MAX_RX_BURST_BUF_SIZE]; /* soft bits normalized 0..1 */
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unsigned nbits; // number of symbols per slot in rxBurst, not counting guard periods
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@ -20,12 +30,17 @@ struct trx_ul_burst_ind {
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double toa; // in symbols
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double noise; // noise level in dBFS
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bool idle; // true if no valid burst is included
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enum Modulation modulation; // modulation type
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uint8_t tss; // training sequence set
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uint8_t tsc; // training sequence code
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float ci; // Carrier-to-Interference ratio, in dB
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};
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bool trxd_send_burst_ind_v0(size_t chan, int fd, const struct trx_ul_burst_ind *bi);
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bool trxd_send_burst_ind_v1(size_t chan, int fd, const struct trx_ul_burst_ind *bi);
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/* The latest supported TRXD header format version */
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#define TRX_DATA_FORMAT_VER 0
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#define TRX_DATA_FORMAT_VER 1
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struct trxd_hdr_common {
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#if OSMO_IS_LITTLE_ENDIAN
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@ -50,3 +65,30 @@ struct trxd_hdr_v0 {
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struct trxd_hdr_v0_specific v0;
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uint8_t soft_bits[0];
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} __attribute__ ((packed));
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#define TRXD_MODULATION_GMSK(ts_set) (0b0000 | (ts_set & 0b0011))
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#define TRXD_MODULATION_8PSK(ts_set) (0b0100 | (ts_set & 0b0001))
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#define TRXD_MODULATION_AQPSK(ts_set) (0b0110 | (ts_set & 0b0001))
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#define TRXD_MODULATION_16QAM(ts_set) (0b1000 | (ts_set & 0b0001))
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#define TRXD_MODULATION_32QAM(ts_set) (0b1010 | (ts_set & 0b0001))
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struct trxd_hdr_v1_specific {
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#if OSMO_IS_LITTLE_ENDIAN
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uint8_t tsc:3,
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modulation:4,
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idle:1;
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#elif OSMO_IS_BIG_ENDIAN
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uint8_t idle:1,
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modulation:4,
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tsc:3;
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#endif
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int16_t ci; /* big endian, in centiBels */
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} __attribute__ ((packed));
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struct trxd_hdr_v1 {
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struct trxd_hdr_common common;
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struct trxd_hdr_v0_specific v0;
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struct trxd_hdr_v1_specific v1;
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uint8_t soft_bits[0];
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} __attribute__ ((packed));
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