Reverting r2342
git-svn-id: http://wush.net/svn/range/software/public/openbts/trunk@2424 19bc5d8c-e614-43d4-8b26-e1612bc8e597
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3ebf98c721
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c8739b8b71
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@ -133,17 +133,17 @@ bool USRPDevice::rx_setFreq(double freq, double *actual_freq)
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if (R==0) return false;
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writeLock.lock();
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m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((R & ~0x3) | 1));
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m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((control & ~0x3) | 0));
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usleep(10000);
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m_uRx->_write_spi(0,SPI_ENABLE_RX_A,SPI_FMT_MSB | SPI_FMT_HDR_0,
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m_uRx->_write_spi(0,SPI_ENABLE_RX_B,SPI_FMT_MSB | SPI_FMT_HDR_0,
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write_it((N & ~0x3) | 2));
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writeLock.unlock();
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if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
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if (m_uRx->read_io(0) & PLL_LOCK_DETECT) return true;
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if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
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if (m_uRx->read_io(1) & PLL_LOCK_DETECT) return true;
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return false;
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}
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@ -197,9 +197,6 @@ bool USRPDevice::make(bool wSkipRx)
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m_uRx.reset();
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return false;
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}
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m_uRx->_write_oe(0,0,0xffff);
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m_uRx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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}
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try {
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@ -216,10 +213,6 @@ bool USRPDevice::make(bool wSkipRx)
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return false;
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}
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m_uTx->_write_oe(0,0,0xffff);
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m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uTx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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if (m_uTx->fpga_master_clock_freq() != masterClockRate)
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{
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LOG(ALERT) << "WRONG FPGA clock freq = " << m_uTx->fpga_master_clock_freq()
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@ -255,13 +248,9 @@ bool USRPDevice::start()
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writeLock.lock();
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// power up and configure daughterboards
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m_uTx->_write_oe(0,0,0xffff);
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m_uTx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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//m_uTx->write_io(0,(POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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//m_uTx->write_io(0,ENABLE,(RX_TXN | ENABLE));
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//m_uTx->write_io(0,(RX_TXN | ENABLE), (RX_TXN | ENABLE));//only for litie
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m_uTx->write_io(0,ENABLE,(POWER_UP|RX_TXN|ENABLE)); /* POWER_UP inverted */
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m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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m_uTx->write_io(0,ENABLE,(RX_TXN | ENABLE));
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m_uTx->_write_fpga_reg(FR_ATR_MASK_0 ,0);//RX_TXN|ENABLE);
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m_uTx->_write_fpga_reg(FR_ATR_TXVAL_0,0);//,0 |ENABLE);
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m_uTx->_write_fpga_reg(FR_ATR_RXVAL_0,0);//,RX_TXN|0);
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@ -275,20 +264,17 @@ bool USRPDevice::start()
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if (!skipRx) {
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writeLock.lock();
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m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 1*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 1*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 1*3,0);
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m_uRx->_write_fpga_reg(41,0);
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m_uRx->_write_fpga_reg(FR_ATR_MASK_0 + 3*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_TXVAL_0 + 3*3,0);
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m_uRx->_write_fpga_reg(FR_ATR_RXVAL_0 + 3*3,0);
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m_uRx->_write_fpga_reg(43,0);
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m_uRx->_write_oe(0,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->write_io(0,(POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
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m_uRx->_write_oe(1,(POWER_UP|RX_TXN|ENABLE), 0xffff);
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m_uRx->write_io(1,(~POWER_UP|RX_TXN|ENABLE),(POWER_UP|RX_TXN|ENABLE));
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//m_uRx->write_io(1,0,RX2_RX1N); // using Tx/Rx/
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m_uRx->write_io(0,RX2_RX1N,RX2_RX1N); // using Rx2
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m_uRx->set_adc_buffer_bypass(0,true);
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m_uRx->set_adc_buffer_bypass(1,true);
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m_uRx->set_pga(0,m_uRx->pga_max()); // should be 20dB
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m_uRx->set_pga(1,m_uRx->pga_max());
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m_uRx->set_mux(0x00000010);
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m_uRx->write_io(1,RX2_RX1N,RX2_RX1N); // using Rx2
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m_uRx->set_adc_buffer_bypass(2,true);
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m_uRx->set_adc_buffer_bypass(3,true);
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m_uRx->set_mux(0x00000032);
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writeLock.unlock();
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// FIXME -- This should be configurable.
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setRxGain(47); //maxRxGain());
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@ -325,7 +311,7 @@ bool USRPDevice::stop()
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// power down
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m_uTx->write_io(0,(~POWER_UP|RX_TXN),(POWER_UP|RX_TXN|ENABLE));
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m_uRx->write_io(0,~POWER_UP,(POWER_UP|ENABLE));
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m_uRx->write_io(1,~POWER_UP,(POWER_UP|ENABLE));
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delete[] currData;
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@ -365,15 +351,15 @@ double USRPDevice::setRxGain(double dB) {
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double rfMax = 70.0;
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if (dB > rfMax) {
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m_uRx->set_pga(0,dB-rfMax);
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m_uRx->set_pga(1,dB-rfMax);
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m_uRx->set_pga(2,dB-rfMax);
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m_uRx->set_pga(3,dB-rfMax);
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dB = rfMax;
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}
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else {
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m_uRx->set_pga(0,0);
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m_uRx->set_pga(1,0);
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m_uRx->set_pga(2,0);
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m_uRx->set_pga(3,0);
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}
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m_uRx->write_aux_dac(0,0,
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m_uRx->write_aux_dac(1,0,
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(int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3));
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LOG(DEBUG) << "Setting DAC voltage to " << (1.2+0.02 - (dB/rfMax)) << " " << (int) ceil((1.2 + 0.02 - (dB/rfMax))*4096.0/3.3);
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@ -552,7 +538,7 @@ int USRPDevice::writeSamples(short *buf, int len, bool *underrun,
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#ifndef SWLOOPBACK
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if (!m_uTx) return 0;
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static uint32_t outData[128*200];
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static uint32_t outData[128*20];
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for (int i = 0; i < len*2; i++) {
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buf[i] = host_to_usrp_short(buf[i]);
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@ -603,7 +589,7 @@ bool USRPDevice::updateAlignment(TIMESTAMP timestamp)
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#ifndef SWLOOPBACK
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short data[] = {0x00,0x02,0x00,0x00};
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uint32_t *wordPtr = (uint32_t *) data;
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//*wordPtr = host_to_usrp_u32(*wordPtr);
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*wordPtr = host_to_usrp_u32(*wordPtr);
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bool tmpUnderrun;
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if (writeSamples((short *) data,1,&tmpUnderrun,timestamp & 0x0ffffffffll,true)) {
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pingTimestamp = timestamp;
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@ -622,7 +608,6 @@ bool USRPDevice::setTxFreq(double wFreq) {
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if (!tx_setFreq(wFreq+1*LO_OFFSET,&actFreq)) return false;
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bool retVal = m_uTx->set_tx_freq(0,(wFreq-actFreq));
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LOG(INFO) << "set TX: " << wFreq-actFreq << " actual TX: " << m_uTx->tx_freq(0);
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//m_uTx->write_io(0,RX_TXN,RX_TXN);
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return retVal;
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};
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@ -637,7 +622,6 @@ bool USRPDevice::setRxFreq(double wFreq) {
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if (!rx_setFreq(wFreq-2*LO_OFFSET,&actFreq)) return false;
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bool retVal = m_uRx->set_rx_freq(0,(wFreq-actFreq));
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LOG(DEBUG) << "set RX: " << wFreq-actFreq << " actual RX: " << m_uRx->rx_freq(0);
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//m_uRx->write_io(0,RX_TXN,RX_TXN);
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return retVal;
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};
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@ -215,10 +215,10 @@ private:
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bool setRxFreq(double wFreq);
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/** Returns the starting write Timestamp*/
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TIMESTAMP initialWriteTimestamp(void) { return 40000;}
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TIMESTAMP initialWriteTimestamp(void) { return 20000;}
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/** Returns the starting read Timestamp*/
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TIMESTAMP initialReadTimestamp(void) { return 40000;}
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TIMESTAMP initialReadTimestamp(void) { return 20000;}
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/** returns the full-scale transmit amplitude **/
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double fullScaleInputValue() {return 13500.0;}
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