Simplify TS alloc: split off RX mask computation
Move computation of RX mask into separate function and document it. This allows to significantly shrink find_multi_slot() function and overall improve code readability. Since the test output requires cosmetic adjustment anyway due to change in the sequence of log messages, use this opportunity to better group and format log message. Change-Id: I731726a096bba7ee97499e5cbe3e7401869d7392 Related: OS#2282
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@ -474,49 +474,28 @@ int alloc_algorithm_a(struct gprs_rlcmac_bts *bts, GprsMs *ms_, struct gprs_rlcm
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*/
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int find_multi_slots(struct gprs_rlcmac_trx *trx, uint8_t mslot_class, uint8_t *ul_slots, uint8_t *dl_slots)
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{
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uint8_t Tx, Sum; /* Maximum Number of Slots: RX, Tx, Sum Rx+Tx */
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uint8_t Tta, Ttb, Tra, Trb; /* Minimum Number of Slots */
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uint8_t Type; /* Type of Mobile */
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uint8_t Tx = mslot_class_get_tx(mslot_class), /* Max number of Tx slots */
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Sum = mslot_class_get_sum(mslot_class); /* Max number of Tx + Rx slots */
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int rx_window, tx_window, pdch_slots;
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static const char *digit[10] = { "0","1","2","3","4","5","6","7","8","9" };
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char slot_info[9] = {0};
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int max_capacity;
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uint8_t max_ul_slots;
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uint8_t max_dl_slots;
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int max_capacity = -1;
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uint8_t max_ul_slots = 0, max_dl_slots = 0;
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unsigned max_slots;
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unsigned ul_ts, dl_ts;
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unsigned num_tx;
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enum {MASK_TT, MASK_TR};
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unsigned mask_sel;
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if (mslot_class)
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LOGP(DRLCMAC, LOGL_DEBUG, "Slot Allocation (Algorithm B) for class %d\n",
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mslot_class);
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Tx = mslot_class_get_tx(mslot_class);
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Sum = mslot_class_get_sum(mslot_class);
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Tta = mslot_class_get_ta(mslot_class);
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Ttb = mslot_class_get_tb(mslot_class);
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/* FIXME: use actual TA offset for computation - make sure to adjust "1 + MS_TO" accordingly
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see also "Offset required" bit in 3GPP TS 24.008 §10.5.1.7 */
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Tra = mslot_class_get_ra(mslot_class, 0);
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Trb = mslot_class_get_rb(mslot_class, 0);
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Type = mslot_class_get_type(mslot_class);
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if (Tx == MS_NA) {
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LOGP(DRLCMAC, LOGL_NOTICE, "Multislot class %d not applicable.\n",
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mslot_class);
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return -EINVAL;
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}
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LOGP(DRLCMAC, LOGL_DEBUG, "- Rx=%d Tx=%d Sum Rx+Tx=%s Tta=%s Ttb=%d "
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" Tra=%d Trb=%d Type=%d\n", mslot_class_get_rx(mslot_class), Tx,
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(Sum == MS_NA) ? "N/A" : digit[Sum],
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(Tta == MS_NA) ? "N/A" : digit[Tta], Ttb, Tra, Trb, Type);
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max_slots = OSMO_MAX(mslot_class_get_rx(mslot_class), Tx);
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if (*dl_slots == 0)
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@ -538,29 +517,12 @@ int find_multi_slots(struct gprs_rlcmac_trx *trx, uint8_t mslot_class, uint8_t *
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/* Check for each UL (TX) slot */
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max_capacity = -1;
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max_ul_slots = 0;
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max_dl_slots = 0;
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/* Iterate through possible numbers of TX slots */
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for (num_tx = 1; num_tx <= mslot_class_get_tx(mslot_class); num_tx += 1) {
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uint16_t tx_valid_win = (1 << num_tx) - 1;
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uint8_t rx_mask[MASK_TR + 1];
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uint8_t rx_mask[MASK_TR+1];
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if (Type == 1) {
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rx_mask[MASK_TT] = (0x100 >> OSMO_MAX(Ttb, Tta)) - 1;
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rx_mask[MASK_TT] &= ~((1 << (Trb + num_tx)) - 1);
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rx_mask[MASK_TR] = (0x100 >> Ttb) - 1;
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rx_mask[MASK_TR] &=
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~((1 << (OSMO_MAX(Trb, Tra) + num_tx)) - 1);
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} else {
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/* Class type 2 MS have independant RX and TX */
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rx_mask[MASK_TT] = 0xff;
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rx_mask[MASK_TR] = 0xff;
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}
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rx_mask[MASK_TT] = (rx_mask[MASK_TT] << 3) | (rx_mask[MASK_TT] >> 5);
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rx_mask[MASK_TR] = (rx_mask[MASK_TR] << 3) | (rx_mask[MASK_TR] >> 5);
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mslot_fill_rx_mask(mslot_class, num_tx, rx_mask);
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/* Rotate group of TX slots: UUU-----, -UUU----, ..., UU-----U */
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for (ul_ts = 0; ul_ts < 8; ul_ts += 1, tx_valid_win <<= 1) {
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@ -629,7 +591,7 @@ int find_multi_slots(struct gprs_rlcmac_trx *trx, uint8_t mslot_class, uint8_t *
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/* Whether to skip this round doesn not only depend on the bit
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* sets but also on mask_sel. Therefore this check must be done
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* before doing the test_and_set_bit shortcut. */
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if (Type == 1) {
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if (mslot_class_get_type(mslot_class) == 1) {
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unsigned slot_sum = rx_slot_count + tx_slot_count;
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/* Assume down+up/dynamic.
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* TODO: For ext-dynamic, down only, up only add more
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@ -681,7 +643,7 @@ int find_multi_slots(struct gprs_rlcmac_trx *trx, uint8_t mslot_class, uint8_t *
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/* Check number of common slots according to TS 54.002, 6.4.2.2 */
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common_slot_count = pcu_bitcount(tx_window & rx_window);
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req_common_slots = OSMO_MIN(tx_slot_count, rx_slot_count);
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if (Type == 1)
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if (mslot_class_get_type(mslot_class) == 1)
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req_common_slots = OSMO_MIN(req_common_slots, 2);
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if (req_common_slots != common_slot_count) {
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@ -21,6 +21,7 @@
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*/
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#include <mslot_class.h>
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#include <gprs_debug.h>
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#include <osmocom/core/utils.h>
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#include <osmocom/core/logging.h>
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@ -170,3 +171,44 @@ uint8_t mslot_class_get_type(uint8_t ms_cl)
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{
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return get_mslot_table(ms_cl)->type;
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}
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/*! Fill in RX mask table for a given MS Class
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*
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* \param[in] ms_cl MS Class pointer
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* \param[in] num_tx Number of TX slots to consider
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* \param[out] rx_mask RX mask table
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*/
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void mslot_fill_rx_mask(uint8_t mslot_class, uint8_t num_tx, uint8_t *rx_mask)
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{
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static const char *digit[10] = { "0","1","2","3","4","5","6","7","8","9" };
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uint8_t Tx = mslot_class_get_tx(mslot_class), /* Max number of Tx slots */
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Sum = mslot_class_get_sum(mslot_class), /* Max number of Tx + Rx slots */
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Type = mslot_class_get_type(mslot_class), /* Type of Mobile */
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Tta = mslot_class_get_ta(mslot_class), /* Minimum number of slots */
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Ttb = mslot_class_get_tb(mslot_class),
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/* FIXME: use actual TA offset for computation - make sure to adjust "1 + MS_TO" accordingly
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see also "Offset required" bit in 3GPP TS 24.008 §10.5.1.7 */
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Tra = mslot_class_get_ra(mslot_class, 0),
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Trb = mslot_class_get_rb(mslot_class, 0);
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if (num_tx == 1) /* it's enough to log this once per TX slot set iteration */
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LOGP(DRLCMAC, LOGL_DEBUG,
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"Rx=%d Tx=%d Sum Rx+Tx=%s, Tta=%s Ttb=%d, Tra=%d Trb=%d, Type=%d\n",
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mslot_class_get_rx(mslot_class), Tx,
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(Sum == MS_NA) ? "N/A" : digit[Sum],
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(Tta == MS_NA) ? "N/A" : digit[Tta], Ttb, Tra, Trb, Type);
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if (Type == 1) {
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rx_mask[MASK_TT] = (0x100 >> OSMO_MAX(Ttb, Tta)) - 1;
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rx_mask[MASK_TT] &= ~((1 << (Trb + num_tx)) - 1);
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rx_mask[MASK_TR] = (0x100 >> Ttb) - 1;
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rx_mask[MASK_TR] &= ~((1 << (OSMO_MAX(Trb, Tra) + num_tx)) - 1);
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} else {
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/* Class type 2 MS have independant RX and TX */
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rx_mask[MASK_TT] = 0xff;
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rx_mask[MASK_TR] = 0xff;
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}
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rx_mask[MASK_TT] = (rx_mask[MASK_TT] << 3) | (rx_mask[MASK_TT] >> 5);
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rx_mask[MASK_TR] = (rx_mask[MASK_TR] << 3) | (rx_mask[MASK_TR] >> 5);
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}
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@ -36,6 +36,8 @@
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#define DEFAULT_MSLOT_CLASS 12
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enum { MASK_TT = 0, MASK_TR = 1 };
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/* multislot class selection routines */
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uint8_t mslot_class_get_ta(uint8_t ms_cl);
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uint8_t mslot_class_get_tb(uint8_t ms_cl);
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@ -46,3 +48,5 @@ uint8_t mslot_class_get_rx(uint8_t ms_cl);
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uint8_t mslot_class_get_sum(uint8_t ms_cl);
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uint8_t mslot_class_get_type(uint8_t ms_cl);
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uint8_t mslot_class_max();
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void mslot_fill_rx_mask(uint8_t mslot_class, uint8_t num_tx, uint8_t *rx_mask);
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@ -3023,12 +3023,12 @@ Modifying MS object, TLLI = 0x00000000, MS class 0 -> 12
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Searching for first unallocated TFI: TRX=0
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Found TFI=0.
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Slot Allocation (Algorithm B) for class 12
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- Rx=4 Tx=4 Sum Rx+Tx=5 Tta=2 Ttb=1 Tra=2 Trb=1 Type=1
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- Skipping TS 0, because not enabled
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- Skipping TS 1, because not enabled
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- Skipping TS 6, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..DDDD.."(TS=7)
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Using 4 slots for DL
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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@ -3062,12 +3062,12 @@ TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL EGPRS) Enabled EGPRS, mode EGPRS
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Searching for first unallocated TFI: TRX=0
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Found TFI=0.
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Slot Allocation (Algorithm B) for class 12
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- Rx=4 Tx=4 Sum Rx+Tx=5 Tta=2 Ttb=1 Tra=2 Trb=1 Type=1
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- Skipping TS 0, because not enabled
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- Skipping TS 1, because not enabled
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- Skipping TS 6, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=4 Sum Rx+Tx=5, Tta=2 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..DDDD.."(TS=7)
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Using 4 slots for DL
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- Reserved DL/UL slots: (TS=0)"..DDCD.."(TS=7)
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@ -5913,12 +5913,12 @@ TBF(TFI=0 TLLI=0x00000000 DIR=DL STATE=NULL EGPRS) Enabled EGPRS, mode EGPRS
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Searching for first unallocated TFI: TRX=0
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Found TFI=0.
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Slot Allocation (Algorithm B) for class 11
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- Rx=4 Tx=3 Sum Rx+Tx=5 Tta=3 Ttb=1 Tra=2 Trb=1 Type=1
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- Skipping TS 0, because not enabled
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- Skipping TS 1, because not enabled
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- Skipping TS 6, because not enabled
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- Skipping TS 7, because not enabled
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- Possible DL/UL slots: (TS=0)"..CCCC.."(TS=7)
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Rx=4 Tx=3 Sum Rx+Tx=5, Tta=3 Ttb=1, Tra=2 Trb=1, Type=1
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- Selected DL slots: (TS=0)"..ddDd.."(TS=7), single
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Using single slot at TS 4 for DL
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- Reserved DL/UL slots: (TS=0)"....C..."(TS=7)
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