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bts_rcv_rach(): Split code paths for Ass and Ass Rej 

The function becomes a bit more long but it's a lot easier to follow.

Change-Id: I80e554315d36a515a7edc9ae51057ce31eb9110d
This commit is contained in:
Pau Espin 2021-10-18 13:29:56 +02:00
parent 9b9f5efb09
commit f5cb4acb14
1 changed files with 28 additions and 26 deletions
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54
src/bts.cpp
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@ -867,13 +867,17 @@ int bts_rcv_rach(struct gprs_rlcmac_bts *bts, const struct rach_ind_params *rip)
struct chan_req_params chan_req = { 0 };
struct gprs_rlcmac_ul_tbf *tbf = NULL;
struct gprs_rlcmac_sba *sba;
struct gprs_rlcmac_pdch *pdch = NULL;
struct gprs_rlcmac_trx *trx = NULL;
struct gprs_rlcmac_pdch *pdch;
struct gprs_rlcmac_trx *trx;
uint32_t sb_fn = 0;
uint8_t usf = 7;
uint8_t tsc = 0;
int plen, rc;
/* Allocate a bit-vector for RR Immediate Assignment [Reject] */
struct bitvec *bv = bitvec_alloc(22, tall_pcu_ctx); /* without plen */
bitvec_unhex(bv, DUMMY_VEC); /* standard '2B'O padding */
bts_do_rate_ctr_inc(bts, CTR_RACH_REQUESTS);
if (rip->is_11bit)
@ -938,36 +942,34 @@ int bts_rcv_rach(struct gprs_rlcmac_bts *bts, const struct rach_ind_params *rip)
}
trx = pdch->trx;
send_imm_ass_rej:
/* Allocate a bit-vector for RR Immediate Assignment [Reject] */
struct bitvec *bv = bitvec_alloc(22, tall_pcu_ctx); /* without plen */
bitvec_unhex(bv, DUMMY_VEC); /* standard '2B'O padding */
if (rc != 0) {
LOGP(DRLCMAC, LOGL_DEBUG, "Tx Immediate Assignment Reject on AGCH\n");
plen = Encoding::write_immediate_assignment_reject(
bv, rip->ra, Fn, rip->burst_type,
(uint8_t)osmo_tdef_get(bts->T_defs_bts, 3142, OSMO_TDEF_S, -1));
bts_do_rate_ctr_inc(bts, CTR_IMMEDIATE_ASSIGN_REJ);
LOGP(DRLCMAC, LOGL_DEBUG, "Tx Immediate Assignment on AGCH: "
"TRX=%u (ARFCN %u) TS=%u TA=%u TSC=%u TFI=%d USF=%d\n",
trx->trx_no, trx->arfcn & ~ARFCN_FLAG_MASK,
pdch->ts_no, ta, tsc, tbf ? tbf->tfi() : -1, usf);
plen = Encoding::write_immediate_assignment(pdch, tbf, bv,
false, rip->ra, Fn, ta, usf, false, sb_fn,
bts_get_ms_pwr_alpha(bts), bts->pcu->vty.gamma, -1,
rip->burst_type);
bts_do_rate_ctr_inc(bts, CTR_IMMEDIATE_ASSIGN_UL_TBF);
if (plen >= 0) {
pcu_l1if_tx_agch(bts, bv, plen);
rc = 0;
} else {
LOGP(DRLCMAC, LOGL_DEBUG, "Tx Immediate Assignment on AGCH: "
"TRX=%u (ARFCN %u) TS=%u TA=%u TSC=%u TFI=%d USF=%d\n",
trx->trx_no, trx->arfcn & ~ARFCN_FLAG_MASK,
pdch->ts_no, ta, tsc, tbf ? tbf->tfi() : -1, usf);
plen = Encoding::write_immediate_assignment(pdch, tbf, bv,
false, rip->ra, Fn, ta, usf, false, sb_fn,
bts_get_ms_pwr_alpha(bts), bts->pcu->vty.gamma, -1,
rip->burst_type);
bts_do_rate_ctr_inc(bts, CTR_IMMEDIATE_ASSIGN_UL_TBF);
rc = plen;
}
bitvec_free(bv);
return rc;
send_imm_ass_rej:
LOGP(DRLCMAC, LOGL_DEBUG, "Tx Immediate Assignment Reject on AGCH\n");
plen = Encoding::write_immediate_assignment_reject(
bv, rip->ra, Fn, rip->burst_type,
(uint8_t)osmo_tdef_get(bts->T_defs_bts, 3142, OSMO_TDEF_S, -1));
bts_do_rate_ctr_inc(bts, CTR_IMMEDIATE_ASSIGN_REJ);
if (plen >= 0)
pcu_l1if_tx_agch(bts, bv, plen);
else
rc = plen;
bitvec_free(bv);
/* rc was already properly set before goto */
return rc;
}