Restructure IA Rest Octets encoders
In preparation for upcoming patches with 11 bit RACH and TA support, let's restructure existing encoders to simplify further modifications: * move consistency checks to top-level Imm. Ass. encoder * use consistent formatting * constify pointers where appropriate * split SBA and MBA encoders into separate functions Those changes also make it obvious which parameters are necessary for Rest Octets in each specific case (DL, UL-SBA, UL-MBA, UL-SBA-EGPRS, UL-MBA-EGPRS). There're no functional code changes so there's no need to adjust tests. Change-Id: I0ad1bc786c3a8055ea9666f64ae82c512bd01603 Related: OS#1548
This commit is contained in:
Max
parent
fc8afc2f33
commit
0160a29b6c
255
src/encoding.cpp
255
src/encoding.cpp
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@ -87,18 +87,11 @@ static inline void write_ta_ie(bitvec *dest, unsigned& wp,
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bitvec_write_field(dest, &wp, ts, 3);
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}
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static int write_ia_rest_downlink(
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gprs_rlcmac_dl_tbf *tbf,
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bitvec * dest, unsigned& wp,
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bool polling, bool ta_valid, uint32_t fn,
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uint8_t alpha, uint8_t gamma, int8_t ta_idx)
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static int write_ia_rest_downlink(const gprs_rlcmac_dl_tbf *tbf, bitvec * dest, bool polling, bool ta_valid,
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uint32_t fn, uint8_t alpha, uint8_t gamma, int8_t ta_idx, unsigned& wp)
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{
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if (!tbf) {
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LOGP(DRLCMACDL, LOGL_ERROR,
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"Cannot encode DL IMMEDIATE ASSIGNMENT without TBF\n");
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return -EINVAL;
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}
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// GSM 04.08 10.5.2.16 IA Rest Octets
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int rc = 0;
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bitvec_write_field(dest, &wp, 3, 2); // "HH"
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bitvec_write_field(dest, &wp, 1, 2); // "01" Packet Downlink Assignment
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bitvec_write_field(dest, &wp,tbf->tlli(),32); // TLLI
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@ -127,128 +120,126 @@ static int write_ia_rest_downlink(
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// bitvec_write_field(dest, &wp,0x1,1); // P0 not present
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// bitvec_write_field(dest, &wp,,0xb,4);
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if (tbf->is_egprs_enabled()) {
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/* see GMS 44.018, 10.5.2.16 */
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bitvec_write_field(dest, &wp, 1, 1); // "H"
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write_ws(dest, &wp, tbf->window_size()); // EGPRS Window Size
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bitvec_write_field(dest, &wp, 0x0, 2); // LINK_QUALITY_MEASUREMENT_MODE
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bitvec_write_field(dest, &wp, 0, 1); // BEP_PERIOD2 not present
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}
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return 0;
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return rc;
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}
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static int write_ia_rest_uplink(
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gprs_rlcmac_ul_tbf *tbf,
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bitvec * dest, unsigned& wp,
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uint8_t usf, uint32_t fn,
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uint8_t alpha, uint8_t gamma, int8_t ta_idx)
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static int write_ia_rest_uplink_sba(bitvec *dest, uint32_t fn, uint8_t alpha, uint8_t gamma, int8_t ta_idx,
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unsigned& wp)
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{
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OSMO_ASSERT(!tbf || !tbf->is_egprs_enabled());
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int rc = 0;
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// GMS 04.08 10.5.2.37b 10.5.2.16
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bitvec_write_field(dest, &wp, 3, 2); // "HH"
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bitvec_write_field(dest, &wp, 0, 2); // "0" Packet Uplink Assignment
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if (tbf == NULL) {
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bitvec_write_field(dest, &wp, 0, 1); // Block Allocation : Single Block Allocation
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if (alpha) {
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bitvec_write_field(dest, &wp,0x1,1); // ALPHA = present
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bitvec_write_field(dest, &wp,alpha,4); // ALPHA = present
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} else
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bitvec_write_field(dest, &wp,0x0,1); // ALPHA = not present
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bitvec_write_field(dest, &wp,gamma,5); // GAMMA power control parameter
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write_tai(dest, wp, ta_idx);
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bitvec_write_field(dest, &wp, 1, 1); // TBF_STARTING_TIME_FLAG
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bitvec_write_field(dest, &wp,(fn / (26 * 51)) % 32,5); // T1'
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bitvec_write_field(dest, &wp,fn % 51,6); // T3
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bitvec_write_field(dest, &wp,fn % 26,5); // T2
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} else {
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bitvec_write_field(dest, &wp, 1, 1); // Block Allocation : Not Single Block Allocation
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bitvec_write_field(dest, &wp, tbf->tfi(), 5); // TFI_ASSIGNMENT Temporary Flow Identity
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bitvec_write_field(dest, &wp, 0, 1); // POLLING
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bitvec_write_field(dest, &wp, 0, 1); // ALLOCATION_TYPE: dynamic
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bitvec_write_field(dest, &wp, usf, 3); // USF
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bitvec_write_field(dest, &wp, 0, 1); // USF_GRANULARITY
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bitvec_write_field(dest, &wp, 0, 1); // "0" power control: Not Present
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bitvec_write_field(dest, &wp, tbf->current_cs().to_num()-1, 2); // CHANNEL_CODING_COMMAND
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bitvec_write_field(dest, &wp, 1, 1); // TLLI_BLOCK_CHANNEL_CODING
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if (alpha) {
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bitvec_write_field(dest, &wp,0x1,1); // ALPHA = present
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bitvec_write_field(dest, &wp,alpha,4); // ALPHA
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} else
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bitvec_write_field(dest, &wp,0x0,1); // ALPHA = not present
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bitvec_write_field(dest, &wp,gamma,5); // GAMMA power control parameter
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/* note: there is no choise for TAI and no starting time */
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bitvec_write_field(dest, &wp, 0, 1); // switch TIMING_ADVANCE_INDEX = off
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bitvec_write_field(dest, &wp, 0, 1); // TBF_STARTING_TIME_FLAG
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}
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return 0;
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bitvec_write_field(dest, &wp, 0, 1); // Block Allocation: Single Block Allocation
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); // ALPHA = present
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bitvec_write_field(dest, &wp, alpha, 4);
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} else
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bitvec_write_field(dest, &wp, 0x0, 1); // ALPHA = not present
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bitvec_write_field(dest, &wp, gamma, 5); // GAMMA power control parameter
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write_tai(dest, wp, ta_idx);
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bitvec_write_field(dest, &wp, 1, 1); // TBF_STARTING_TIME_FLAG
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bitvec_write_field(dest, &wp, (fn / (26 * 51)) % 32, 5); // T1'
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bitvec_write_field(dest, &wp, fn % 51, 6); // T3
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bitvec_write_field(dest, &wp, fn % 26, 5); // T2
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return rc;
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}
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static int write_ia_rest_egprs_uplink(
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gprs_rlcmac_ul_tbf *tbf,
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bitvec * dest, unsigned& wp,
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uint8_t usf, uint32_t fn,
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uint8_t alpha, uint8_t gamma, int8_t ta_idx,
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enum ph_burst_type burst_type, uint16_t ra)
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static int write_ia_rest_uplink_mba(const gprs_rlcmac_ul_tbf *tbf, bitvec *dest, uint8_t usf,
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uint8_t alpha, uint8_t gamma, unsigned& wp)
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{
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uint8_t extended_ra = 0;
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int rc = 0;
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extended_ra = (ra & 0x1F);
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bitvec_write_field(dest, &wp, 1, 1); // Block Allocation: Not Single Block Allocation
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bitvec_write_field(dest, &wp, tbf->tfi(), 5); // TFI_ASSIGNMENT Temporary Flow Identity
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bitvec_write_field(dest, &wp, 0, 1); // POLLING
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bitvec_write_field(dest, &wp, 0, 1); // ALLOCATION_TYPE: dynamic
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bitvec_write_field(dest, &wp, usf, 3); // USF
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bitvec_write_field(dest, &wp, 0, 1); // USF_GRANULARITY
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bitvec_write_field(dest, &wp, 0, 1); // "0" power control: Not Present
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bitvec_write_field(dest, &wp, tbf->current_cs().to_num() - 1, 2); // CHANNEL_CODING_COMMAND
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bitvec_write_field(dest, &wp, 1, 1); // TLLI_BLOCK_CHANNEL_CODING
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); // ALPHA = present
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bitvec_write_field(dest, &wp, alpha, 4); // ALPHA
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} else
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bitvec_write_field(dest, &wp, 0x0, 1); // ALPHA = not present
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bitvec_write_field(dest, &wp, 1, 2); /* LH */
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bitvec_write_field(dest, &wp, 0, 2); /* 0 EGPRS Uplink Assignment */
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bitvec_write_field(dest, &wp, extended_ra, 5); /* Extended RA */
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bitvec_write_field(dest, &wp, 0, 1); /* Access technology Request */
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bitvec_write_field(dest, &wp, gamma, 5); // GAMMA power control parameter
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if (tbf == NULL) {
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/* note: there is no choise for TAI and no starting time */
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bitvec_write_field(dest, &wp, 0, 1); // switch TIMING_ADVANCE_INDEX = off
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bitvec_write_field(dest, &wp, 0, 1); // TBF_STARTING_TIME_FLAG
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bitvec_write_field(dest, &wp, 0, 1); /* multiblock allocation */
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return rc;
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}
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); /* ALPHA =yes */
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bitvec_write_field(dest, &wp, alpha, 4); /* ALPHA */
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} else {
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bitvec_write_field(dest, &wp, 0x0, 1); /* ALPHA = no */
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}
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static int write_ia_rest_egprs_uplink_mba(bitvec * dest, uint32_t fn, uint8_t alpha, uint8_t gamma, unsigned& wp)
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{
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int rc = 0;
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bitvec_write_field(dest, &wp, gamma, 5); /* GAMMA power contrl */
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bitvec_write_field(dest, &wp, (fn / (26 * 51)) % 32, 5);/* T1' */
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bitvec_write_field(dest, &wp, fn % 51, 6); /* T3 */
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bitvec_write_field(dest, &wp, fn % 26, 5); /* T2 */
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bitvec_write_field(dest, &wp, 0, 2); /* Radio block allocation */
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bitvec_write_field(dest, &wp, 0, 1);
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bitvec_write_field(dest, &wp, 0, 1); /* multiblock allocation */
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); /* ALPHA =yes */
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bitvec_write_field(dest, &wp, alpha, 4); /* ALPHA */
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} else {
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bitvec_write_field(dest, &wp, 1, 1); /* single block alloc */
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bitvec_write_field(dest, &wp, tbf->tfi(), 5);/* TFI assignment */
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bitvec_write_field(dest, &wp, 0, 1); /* polling bit */
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bitvec_write_field(dest, &wp, 0, 1); /* constant */
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bitvec_write_field(dest, &wp, usf, 3); /* USF bit */
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bitvec_write_field(dest, &wp, 0, 1); /* USF granularity */
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bitvec_write_field(dest, &wp, 0, 1); /* P0 */
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/* MCS */
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bitvec_write_field(dest, &wp, tbf->current_cs().to_num()-1, 4);
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/* tlli channel block */
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bitvec_write_field(dest, &wp, tbf->tlli(), 1);
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bitvec_write_field(dest, &wp, 0, 1); /* BEP period present */
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bitvec_write_field(dest, &wp, 0, 1); /* resegmentation */
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write_ws(dest, &wp, tbf->window_size()); /* EGPRS window size */
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); /* ALPHA =yes */
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bitvec_write_field(dest, &wp, alpha, 4); /* ALPHA */
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} else {
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bitvec_write_field(dest, &wp, 0x0, 1); /* ALPHA = no */
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}
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bitvec_write_field(dest, &wp, gamma, 5); /* GAMMA power contrl */
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bitvec_write_field(dest, &wp, 0, 1); /* TIMING_ADVANCE_INDEX */
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bitvec_write_field(dest, &wp, 0, 1); /* TBF_STARTING_TIME_FLAG */
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bitvec_write_field(dest, &wp, 0, 1); /* NULL */
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bitvec_write_field(dest, &wp, 0x0, 1); /* ALPHA = no */
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}
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return 0;
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bitvec_write_field(dest, &wp, gamma, 5); /* GAMMA power contrl */
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bitvec_write_field(dest, &wp, (fn / (26 * 51)) % 32, 5);/* T1' */
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bitvec_write_field(dest, &wp, fn % 51, 6); /* T3 */
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bitvec_write_field(dest, &wp, fn % 26, 5); /* T2 */
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bitvec_write_field(dest, &wp, 0, 2); /* Radio block allocation */
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bitvec_write_field(dest, &wp, 0, 1);
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return rc;
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}
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static int write_ia_rest_egprs_uplink_sba(const gprs_rlcmac_ul_tbf *tbf, bitvec * dest, uint8_t usf,
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uint8_t alpha, uint8_t gamma, unsigned& wp)
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{
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int rc = 0;
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bitvec_write_field(dest, &wp, 1, 1); /* single block allocation */
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bitvec_write_field(dest, &wp, tbf->tfi(), 5); /* TFI assignment */
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bitvec_write_field(dest, &wp, 0, 1); /* polling bit */
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bitvec_write_field(dest, &wp, 0, 1); /* constant */
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bitvec_write_field(dest, &wp, usf, 3); /* USF bit */
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bitvec_write_field(dest, &wp, 0, 1); /* USF granularity */
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bitvec_write_field(dest, &wp, 0, 1); /* P0 */
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/* MCS */
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bitvec_write_field(dest, &wp, tbf->current_cs().to_num() - 1, 4);
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/* TLLI channel block */
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bitvec_write_field(dest, &wp, tbf->tlli(), 1);
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bitvec_write_field(dest, &wp, 0, 1); /* BEP period present */
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bitvec_write_field(dest, &wp, 0, 1); /* resegmentation */
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write_ws(dest, &wp, tbf->window_size()); /* EGPRS window size */
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if (alpha) {
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bitvec_write_field(dest, &wp, 0x1, 1); /* ALPHA = yes */
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bitvec_write_field(dest, &wp, alpha, 4); /* ALPHA */
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} else {
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bitvec_write_field(dest, &wp, 0x0, 1); /* ALPHA = no */
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}
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bitvec_write_field(dest, &wp, gamma, 5); /* GAMMA power contrl */
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bitvec_write_field(dest, &wp, 0, 1); /* TIMING_ADVANCE_INDEX */
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bitvec_write_field(dest, &wp, 0, 1); /* TBF_STARTING_TIME_FLAG */
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bitvec_write_field(dest, &wp, 0, 1); /* NULL */
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return rc;
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}
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/*
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@ -396,19 +387,37 @@ int Encoding::write_immediate_assignment(
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plen = wp / 8;
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if (downlink)
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rc = write_ia_rest_downlink(as_dl_tbf(tbf), dest, wp,
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polling, gsm48_ta_is_valid(ta), fn,
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alpha, gamma, ta_idx);
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else if (((burst_type == GSM_L1_BURST_TYPE_ACCESS_1) ||
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(burst_type == GSM_L1_BURST_TYPE_ACCESS_2)))
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rc = write_ia_rest_egprs_uplink(as_ul_tbf(tbf), dest, wp,
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usf, fn,
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alpha, gamma, ta_idx, burst_type, ra);
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else
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rc = write_ia_rest_uplink(as_ul_tbf(tbf), dest, wp,
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usf, fn,
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alpha, gamma, ta_idx);
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/* 3GPP TS 44.018 §10.5.2.16 IA Rest Octets */
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if (downlink) {
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if (!as_dl_tbf(tbf)) {
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LOGP(DRLCMACDL, LOGL_ERROR, "Cannot encode DL IMMEDIATE ASSIGNMENT without TBF\n");
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return -EINVAL;
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}
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rc = write_ia_rest_downlink(as_dl_tbf(tbf), dest, polling, gsm48_ta_is_valid(ta), fn, alpha, gamma,
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ta_idx, wp);
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} else if (((burst_type == GSM_L1_BURST_TYPE_ACCESS_1) || (burst_type == GSM_L1_BURST_TYPE_ACCESS_2))) {
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bitvec_write_field(dest, &wp, 1, 2); /* LH */
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bitvec_write_field(dest, &wp, 0, 2); /* 0 EGPRS Uplink Assignment */
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bitvec_write_field(dest, &wp, ra & 0x1F, 5); /* Extended RA */
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bitvec_write_field(dest, &wp, 0, 1); /* Access technology Request */
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if (as_ul_tbf(tbf) != NULL) {
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rc = write_ia_rest_egprs_uplink_sba(as_ul_tbf(tbf), dest, usf, alpha, gamma, wp);
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} else {
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rc = write_ia_rest_egprs_uplink_mba(dest, fn, alpha, gamma, wp);
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}
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} else {
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OSMO_ASSERT(!tbf || !tbf->is_egprs_enabled());
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bitvec_write_field(dest, &wp, 3, 2); // "HH"
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bitvec_write_field(dest, &wp, 0, 2); // "0" Packet Uplink Assignment
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if (as_ul_tbf(tbf) != NULL) {
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rc = write_ia_rest_uplink_mba(as_ul_tbf(tbf), dest, usf, alpha, gamma, wp);
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} else {
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rc = write_ia_rest_uplink_sba(dest, fn, alpha, gamma, ta_idx, wp);
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}
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}
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if (rc < 0) {
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LOGP(DRLCMAC, LOGL_ERROR,
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