Vadim Yanitskiy
c78aeb7cc6
A comment in f_TC_rsl_ms_pwr_dyn_up() states: > By default, the MS power loop gets triggered every 4th SACCH block (1.92s). > We need 9 * 4 dB steps to get from 0 dBm to 33 dBm, so 9 * 1.92s total. > Add an extra offset to avoid race conditions: +1.92s. so the alt statement is expected to block for 19.2s, while the guard timer is set to 20.0s by default. This is not enough, given that f_TC_rsl_ms_pwr_dyn_up() also needs to wait for the first SACCH block before entering the alt statement. Let's give it more time to run in order to avoid sporadic failures. Change-Id: Ib7de8383c95ac9e00560f786ec4c56f79f7d81bc Related: OS#5635 |
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.. | ||
BTS_Tests.cfg | ||
BTS_Tests.default | ||
BTS_Tests.ttcn | ||
BTS_Tests_LAPDm.ttcn | ||
BTS_Tests_OML.ttcn | ||
BTS_Tests_SMSCB.ttcn | ||
BTS_Tests_VAMOS.ttcn | ||
BTS_Tests_perf.ttcn | ||
README.md | ||
expected-results.xml | ||
gen_links.sh | ||
osmo-bsc.cfg | ||
osmo-bts.cfg | ||
regen_makefile.sh |
README.md
BTS_Tests.ttcn
- external interfaces
- A-bis side: RSL (emulates BSC-side server)
- Um side: L1CTL to control MS
- PCU side: pcu_socket
- VTY
- CTRL
{% dot bts_tests.svg digraph G { rankdir=LR; { rank=same; BTS, BSC}; BTS [label="IUT\nosmo-bts-trx",shape="box"]; ATS [label="ATS\nBTS_Tests.ttcn"]; BSC [label="osmo-bsc\nOML only"]; BTS -> fake_trx [label="bursts"]; fake_trx -> trxcon [label="bursts"]; trxcon -> ATS [label="GSM MAC blocks"];
BTS -> BSC [label="A-bis OML"]; BTS -> ATS [label="A-bis RSL"];
ATS -> BTS [label="pcu_sock"]; ATS -> BSC [label="VTY"]; ATS -> BTS [label="CTRL"]; } %}