library/L1CTL_PortType: fix indention in alt() statements

Change-Id: Ic13c2acbe1379558884fa7d11ba0b52ef31544f3
This commit is contained in:
Vadim Yanitskiy 2020-10-19 13:10:23 +07:00
parent c7ef03057f
commit e7c4a99160
1 changed files with 53 additions and 53 deletions

View File

@ -90,12 +90,12 @@ module L1CTL_PortType {
T.start
pt.send(ts_L1CTL_RACH_REQ(ra, combined, offset, chan_nr, link_id))
alt {
[] pt.receive(tr_L1CTL_RACH_CONF) -> value rc { fn := rc.dl_info.frame_nr };
[] pt.receive { repeat; };
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_RACH_CONF");
mtc.stop;
}
[] pt.receive(tr_L1CTL_RACH_CONF) -> value rc { fn := rc.dl_info.frame_nr };
[] pt.receive { repeat; };
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_RACH_CONF");
mtc.stop;
}
}
return fn;
}
@ -111,12 +111,12 @@ module L1CTL_PortType {
T.start;
pt.send(ts_L1CTL_EXT_RACH_REQ(ra11, seq, combined, offset));
alt {
[] pt.receive(tr_L1CTL_RACH_CONF) -> value rc { fn := rc.dl_info.frame_nr };
[] pt.receive { repeat; };
[] T.timeout {
setverdict(fail, "Timeout waiting for (extended) L1CTL_RACH_CONF");
mtc.stop;
}
[] pt.receive(tr_L1CTL_RACH_CONF) -> value rc { fn := rc.dl_info.frame_nr };
[] pt.receive { repeat; };
[] T.timeout {
setverdict(fail, "Timeout waiting for (extended) L1CTL_RACH_CONF");
mtc.stop;
}
}
return fn;
@ -140,20 +140,20 @@ module L1CTL_PortType {
T.start;
alt {
[] pt.receive(tr_L1CTL_DATA_IND(t_RslChanNr_PCH_AGCH(0))) -> value dl {
rr := dec_GsmRrMessage(dl.payload.data_ind.payload);
log("PCH/AGCH DL RR: ", rr);
if (match(rr, rr_imm_ass)) {
log("Received IMM.ASS for our RACH!");
} else {
repeat;
}
};
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for IMM ASS");
mtc.stop;
}
[] pt.receive(tr_L1CTL_DATA_IND(t_RslChanNr_PCH_AGCH(0))) -> value dl {
rr := dec_GsmRrMessage(dl.payload.data_ind.payload);
log("PCH/AGCH DL RR: ", rr);
if (match(rr, rr_imm_ass)) {
log("Received IMM.ASS for our RACH!");
} else {
repeat;
}
};
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for IMM ASS");
mtc.stop;
}
}
T.stop;
return rr.payload.imm_ass;
@ -167,21 +167,21 @@ module L1CTL_PortType {
timer T := 10.0;
T.start;
alt {
[] pt.receive(tr_L1CTL_DATA_IND(t_RslChanNr_PCH_AGCH(0))) -> value dl {
/* TODO: use decmatch tr_IaRestOctets_DLAss(...) instead */
rr := dec_GsmRrMessage(dl.payload.data_ind.payload);
log("PCH/AGCN DL RR: ", rr);
if (match(rr, tr_IMM_TBF_ASS(dl := true, rest := rest))) {
log("Received IMM.ASS for our TLLI!");
} else {
repeat;
}
};
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for TBF IMM ASS");
mtc.stop;
}
[] pt.receive(tr_L1CTL_DATA_IND(t_RslChanNr_PCH_AGCH(0))) -> value dl {
/* TODO: use decmatch tr_IaRestOctets_DLAss(...) instead */
rr := dec_GsmRrMessage(dl.payload.data_ind.payload);
log("PCH/AGCN DL RR: ", rr);
if (match(rr, tr_IMM_TBF_ASS(dl := true, rest := rest))) {
log("Received IMM.ASS for our TLLI!");
} else {
repeat;
}
};
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for TBF IMM ASS");
mtc.stop;
}
}
T.stop;
return rr.payload.imm_ass;
@ -192,12 +192,12 @@ module L1CTL_PortType {
T.start;
pt.send(ts_L1CTL_TBF_CFG_REQ(is_uplink, tfi_usf));
alt {
[] pt.receive(tr_L1CTL_TBF_CFG_CONF(is_uplink)) {}
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_TBF_CFG_CONF");
mtc.stop;
};
[] pt.receive(tr_L1CTL_TBF_CFG_CONF(is_uplink)) {}
[] pt.receive { repeat };
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_TBF_CFG_CONF");
mtc.stop;
};
}
T.stop;
}
@ -236,12 +236,12 @@ module L1CTL_PortType {
pt.send(t_L1ctlResetReq(res_type));
T.start;
alt {
[] pt.receive(tr_L1CTL_MsgType(L1CTL_RESET_CONF)) { }
[] pt.receive { repeat; }
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_RESET_CONF");
mtc.stop;
}
[] pt.receive(tr_L1CTL_MsgType(L1CTL_RESET_CONF)) { }
[] pt.receive { repeat; }
[] T.timeout {
setverdict(fail, "Timeout waiting for L1CTL_RESET_CONF");
mtc.stop;
}
}
}