2018-05-08 15:32:06 +00:00
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<?xml version="1.0"?>
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2018-09-06 12:13:34 +00:00
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<testsuite name='Titan' tests='85' failures='1' errors='0' skipped='1' inconc='0' time='MASKED'>
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2018-05-08 15:32:06 +00:00
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<testcase classname='BTS_Tests' name='TC_chan_act_stress' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_act_react' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_deact_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_act_wrong_nr' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_deact_sacch' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_sacch_filling' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_sacch_info_mod' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_sacch_multi' time='MASKED'/>
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2018-07-25 09:50:33 +00:00
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<testcase classname='BTS_Tests' name='TC_sacch_multi_chg' time='MASKED'/>
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2018-05-08 15:32:06 +00:00
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<testcase classname='BTS_Tests' name='TC_rach_content' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rach_count' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rach_max_ta' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_meas_res_sign_tchf' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_meas_res_sign_tchh' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_meas_res_sign_sdcch4' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_meas_res_sign_sdcch8' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_meas_res_sign_tchh_toa256' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_conn_fail_crit' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_paging_imsi_80percent' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_paging_tmsi_80percent' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_paging_imsi_200percent' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_paging_tmsi_200percent' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rsl_protocol_error' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rsl_mand_ie_error' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rsl_ie_content_error' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_default' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_1' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_2bis' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_2ter' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_2ter_2bis' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_2quater' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_13' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_si_sched_13_2bis_2ter_2quater' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_ipa_dlcx_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_ipa_crcx_twice_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_ipa_crcx_mdcx_dlcx_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_ipa_crcx_mdcx_mdcx_dlcx_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_ipa_crcx_sdcch_not_active' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_act_req' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_ts' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_bts' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_act_req_wrong_trx' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_deact_req' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_deact_req_wrong_ts' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_ver_si13' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_bts' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_trx' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_wrong_ts' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_ts_inactive' time='MASKED'>
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<skipped>no verdict</skipped>
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</testcase>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_pdtch' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_ptcch' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_agch' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_data_req_imm_ass_pch' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_rach_content' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_pcu_paging_from_rsl' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_act_deact' time='MASKED'/>
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2018-05-10 21:11:54 +00:00
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<testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_unsol_deact' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_double_act' time='MASKED'/>
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2018-05-08 15:32:06 +00:00
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<testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_tchf_act' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_osmo_pdch_tchh_act' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_act_deact' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_tchf_act' time='MASKED'/>
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2018-05-10 21:11:54 +00:00
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<testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_tchf_act_pdch_act_nack' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_dyn_ipa_pdch_act_tchf_act_nack' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_est_ind' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_est_req_DCCH_3' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_est_req_ACCH_3' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_rel_ind_DCCH_0' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_rel_ind_DCCH_3' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_rel_ind_ACCH_0' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_rel_ind_ACCH_3' time='MASKED'/>
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2018-05-14 12:20:09 +00:00
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<testcase classname='BTS_Tests' name='TC_rll_rel_req' time='MASKED'/>
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2018-05-10 21:11:54 +00:00
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<testcase classname='BTS_Tests' name='TC_rll_unit_data_req_DCCH' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_unit_data_req_ACCH' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_unit_data_ind_DCCH' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_rll_unit_data_ind_ACCH' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_act_a51' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_act_a52' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_chan_act_a53' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_encr_cmd_a51' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_encr_cmd_a52' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_encr_cmd_a53' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_lapdm_selftest' time='MASKED'/>
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2018-08-07 16:12:59 +00:00
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<testcase classname='BTS_Tests' name='TC_tch_sign_l2_fill_frame' time='MASKED'/>
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<testcase classname='BTS_Tests' name='TC_tch_sign_l2_fill_frame_dtxd' time='MASKED'>
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2018-09-06 12:13:34 +00:00
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<failure type='fail-verdict'>Not enough fill frames received
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2018-08-07 16:12:59 +00:00
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BTS_Tests.ttcn:MASKED BTS_Tests control part
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BTS_Tests.ttcn:MASKED TC_tch_sign_l2_fill_frame_dtxd testcase
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</failure>
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</testcase>
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2018-05-08 15:32:06 +00:00
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</testsuite>
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