41 lines
864 B
Verilog
41 lines
864 B
Verilog
/*
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* soc_bram.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2020 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module soc_bram #(
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parameter integer SIZE = 256,
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parameter integer AW = $clog2(SIZE),
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parameter INIT_FILE = ""
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)(
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input wire [AW-1:0] addr,
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output reg [31:0] rdata,
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input wire [31:0] wdata,
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input wire [ 3:0] wmsk,
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input wire we,
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input wire clk
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);
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(* no_rw_check *)
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reg [31:0] mem [0:SIZE-1];
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initial
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if (INIT_FILE != "")
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$readmemh(INIT_FILE, mem);
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always @(posedge clk) begin
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rdata <= mem[addr];
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if (we & ~wmsk[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
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if (we & ~wmsk[1]) mem[addr][15: 8] <= wdata[15: 8];
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if (we & ~wmsk[2]) mem[addr][23:16] <= wdata[23:16];
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if (we & ~wmsk[3]) mem[addr][31:24] <= wdata[31:24];
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end
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endmodule // soc_bram
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