65 lines
839 B
Verilog
65 lines
839 B
Verilog
/*
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* top_tb.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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module top_tb;
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// Signals
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// -------
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wire [3:0] spi_io;
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wire spi_cs_n;
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wire spi_clk;
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wire usb_dp;
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wire usb_dn;
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wire usb_pu;
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// Setup recording
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// ---------------
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initial begin
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$dumpfile("top_tb.vcd");
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$dumpvars(0,top_tb);
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# 2000000 $finish;
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end
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// DUT
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// ---
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top dut_I (
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.spi_io (spi_io),
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.spi_clk (spi_clk),
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.spi_cs_n (spi_cs_n),
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.usb_dp (usb_dp),
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.usb_dn (usb_dn),
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.usb_pu (usb_pu)
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);
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// Support
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// -------
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pullup(usb_dp);
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pullup(usb_dn);
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spiflash flash_I (
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.csb (spi_cs_n),
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.clk (spi_clk),
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.io0 (spi_io[0]),
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.io1 (spi_io[1]),
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.io2 (spi_io[2]),
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.io3 (spi_io[3])
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);
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endmodule // top_tb
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