155 lines
2.6 KiB
Verilog
155 lines
2.6 KiB
Verilog
/*
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* led_ctrl_tb.v
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*
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* vim: ts=4 sw=4
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*
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* Copyright (C) 2022-2023 Sylvain Munaut <tnt@246tNt.com>
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* SPDX-License-Identifier: CERN-OHL-P-2.0
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*/
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`default_nettype none
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`timescale 1ns / 100ps
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module led_ctrl_tb;
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// Signals
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// -------
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// DUT
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wire [13:0] led_a;
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wire [2:0] led_c;
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wire trig_out;
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// Wishbone interface
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reg [31:0] wb_wdata;
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wire [31:0] wb_rdata;
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reg [15:0] wb_addr;
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reg wb_we;
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reg wb_cyc;
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wire wb_ack;
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// Clocks / Sync
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reg pll_lock = 1'b0;
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reg led_clk = 1'b0;
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wire led_rst;
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reg [3:0] led_rst_cnt = 4'h8;
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reg wb_clk = 1'b0;
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wire wb_rst;
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reg [3:0] wb_rst_cnt = 4'h8;
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// Recording setup
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// ---------------
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initial begin
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$dumpfile("led_ctrl_tb.vcd");
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$dumpvars(0,led_ctrl_tb);
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end
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// DUT
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// ---
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led_ctrl dut_I (
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.led_a (led_a),
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.led_c (led_c),
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.led_clk (led_clk),
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.led_rst (led_rst),
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.trig_out (trig_out),
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.wb_addr (wb_addr),
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.wb_rdata (wb_rdata),
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.wb_wdata (wb_wdata),
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.wb_we (wb_we),
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.wb_cyc (wb_cyc),
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.wb_ack (wb_ack),
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.wb_clk (wb_clk),
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.wb_rst (wb_rst)
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);
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// Stimulus
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// --------
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task wb_write;
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input [15:0] addr;
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input [31:0] data;
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begin
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wb_addr <= addr;
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wb_wdata <= data;
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wb_we <= 1'b1;
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wb_cyc <= 1'b1;
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while (~wb_ack)
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@(posedge wb_clk);
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wb_addr <= 4'hx;
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wb_wdata <= 32'hxxxxxxxx;
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wb_we <= 1'bx;
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wb_cyc <= 1'b0;
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@(posedge wb_clk);
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end
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endtask
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initial begin
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// Defaults
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wb_addr <= 4'hx;
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wb_wdata <= 32'hxxxxxxxx;
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wb_we <= 1'bx;
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wb_cyc <= 1'b0;
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@(negedge wb_rst);
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@(negedge led_rst);
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@(posedge wb_clk);
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// Write to frame memory
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// Anode 4
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// C0 [00-7f] (all ON)
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// C1 (all OFF)
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// C2 [40-4f] (16 cycles)
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wb_write(16'h0200, 32'h7f_00_00_04);
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wb_write(16'h0201, 32'h4f_40_00_7f);
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wb_write(16'h0202, 32'h01_01_00_0a);
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wb_write(16'h0203, 32'h01_00_00_01);
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// Enable
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wb_write(16'h0000, 32'hc0000007);
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end
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// Clock / Reset
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// -------------
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// Clocks
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initial begin
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# 200 pll_lock = 1'b1;
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# 1000000 $finish;
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//# 35000000 $finish;
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end
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always #20 wb_clk = ~wb_clk; // 25 MHz
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always #83 led_clk = ~led_clk; // 6 MHz
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// Reset
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always @(posedge wb_clk or negedge pll_lock)
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if (~pll_lock)
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wb_rst_cnt <= 4'h8;
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else if (wb_rst_cnt[3])
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wb_rst_cnt <= wb_rst_cnt + 1;
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assign wb_rst = wb_rst_cnt[3];
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always @(posedge led_clk or negedge pll_lock)
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if (~pll_lock)
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led_rst_cnt <= 4'h8;
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else if (led_rst_cnt[3])
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led_rst_cnt <= led_rst_cnt + 1;
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assign led_rst = led_rst_cnt[3];
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endmodule
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