Sylvain Munaut 2188b231be gateware: Switch clk_sys to 12 MHz
This actually helps save a bit of power (at least for sysmgr_3) since
the "always-on" clk_base is slower.

The SoC needs more time to compute frames, but the same number of
cycles so that doesn't change the power on clk_sys itself really.

This will also be helpful for upcoming commits where we switch to
a Vex that has better IPC but doesn't easily meet 24 MHz constraint.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-03-22 21:54:35 +01:00
clocks.py gateware: Switch clk_sys to 12 MHz 2023-03-22 21:54:35 +01:00
top-xmas-snoopy.pcf gateware: Set explicit 100K pullup for pwr_usb_n/pwr_chg_n 2023-03-16 09:59:06 +01:00