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Sylvain Munaut 2188b231be gateware: Switch clk_sys to 12 MHz ... This actually helps save a bit of power (at least for sysmgr_3) since the "always-on" clk_base is slower. The SoC needs more time to compute frames, but the same number of cycles so that doesn't change the power on clk_sys itself really. This will also be helpful for upcoming commits where we switch to a Vex that has better IPC but doesn't easily meet 24 MHz constraint. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2 months ago
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clocks.py	gateware: Switch clk_sys to 12 MHz	2 months ago
top-xmas-snoopy.pcf	gateware: Set explicit 100K pullup for pwr_usb_n/pwr_chg_n	3 months ago