/* * top.v * * vim: ts=4 sw=4 * * Copyright (C) 2019-2020 Sylvain Munaut * SPDX-License-Identifier: CERN-OHL-P-2.0 */ `default_nettype none module top ( // SPI inout wire [3:0] spi_io, output wire spi_clk, output wire spi_cs_n, // USB inout wire usb_dp, inout wire usb_dn, output wire usb_pu, // Power input wire pwr_usb_n, input wire pwr_chg_n, output wire pwr_off, // Buttons input wire [1:0] btn, // I2C inout wire scl, inout wire sda, // Speaker output wire hp_p, output wire hp_n, // LED matrix output wire [13:0] led_a, output wire [2:0] led_c ); localparam integer WN = 6; genvar i; // Signals // ------- // Wishbone wire [15:0] wb_addr; wire [31:0] wb_rdata [0:WN-1]; wire [31:0] wb_wdata; wire [3:0] wb_wmsk; wire [WN-1:0] wb_cyc; wire wb_we; wire [WN-1:0] wb_ack; wire [(32*WN)-1:0] wb_rdata_flat; // I2C wire i2c_scl_oe; wire i2c_scl_i; wire i2c_sda_oe; wire i2c_sda_i; // USB Core // Wishbone in 48 MHz domain wire [11:0] ub_addr; wire [15:0] ub_wdata; wire [15:0] ub_rdata; wire ub_cyc; wire ub_we; wire ub_ack; // EP Buffer wire [ 8:0] ep_tx_addr_0; wire [31:0] ep_tx_data_0; wire ep_tx_we_0; wire [ 8:0] ep_rx_addr_0; wire [31:0] ep_rx_data_1; wire ep_rx_re_0; // Clock Control wire wakeup; wire sys_start; wire sys_stop; wire usb_ena; // Clock / Reset wire clk_led; wire rst_led; wire clk_sys; wire rst_sys; wire clk_usb; wire rst_usb; // SoC // --- soc_picorv32_base #( .WB_N (WN), .WB_DW (32), .WB_AW (16), .BRAM_AW (8), // 1k BRAM .SPRAM_AW (14) // 64k SPRAM ) base_I ( .wb_addr (wb_addr), .wb_rdata (wb_rdata_flat), .wb_wdata (wb_wdata), .wb_wmsk (wb_wmsk), .wb_we (wb_we), .wb_cyc (wb_cyc), .wb_ack (wb_ack), .clk (clk_sys), .rst (rst_sys) ); for (i=0; i