Commit Graph

4 Commits

Author SHA1 Message Date
Sylvain Munaut 2188b231be gateware: Switch clk_sys to 12 MHz
This actually helps save a bit of power (at least for sysmgr_3) since
the "always-on" clk_base is slower.

The SoC needs more time to compute frames, but the same number of
cycles so that doesn't change the power on clk_sys itself really.

This will also be helpful for upcoming commits where we switch to
a Vex that has better IPC but doesn't easily meet 24 MHz constraint.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-03-22 21:54:35 +01:00
Sylvain Munaut c21605e845 gateware/rtl: Fix sysmgr_2 PLL output order and gating
For some reasons the ports were not in order and also the gating
was applied to the wrong port.

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-03-21 13:04:20 +01:00
Sylvain Munaut b2d95779c6 gateware/sysmgr: Make sure sys_start _always_ forces system clock ON
Before it was only sensitive to rising edge. But for the "start" we
actually want to force it on if active to avoid race condition in the
software where:

- CPU clears the condition of the wakeup
- New wake up event happens right after it
- CPU asks for shutdown
- And then no rising edge happens because wakeup is already high

For shutdown it's good that it's rising edge dependent since the
OFF command signal _might_ stay high if the system clock shuts down

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-03-16 09:59:06 +01:00
Sylvain Munaut c85dc29b06 gateware: Initial import of the FPGA gateware
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2023-03-11 23:54:12 +01:00