diff --git a/gateware/data/clocks.py b/gateware/data/clocks.py
index 711319f..e88eeb6 100644
--- a/gateware/data/clocks.py
+++ b/gateware/data/clocks.py
@@ -1,4 +1,4 @@
 ctx.addClock("clk_led",  6)
-ctx.addClock("clk_sys", 24)
+ctx.addClock("clk_sys", 12)
 ctx.addClock("clk_usb", 48)
 ctx.addClock("pmu_I.btn_clk", 20)	# Just to avoid screwing the histogram
diff --git a/gateware/rtl/sysmgr_1.v b/gateware/rtl/sysmgr_1.v
index fe88ed6..7ce2e4a 100644
--- a/gateware/rtl/sysmgr_1.v
+++ b/gateware/rtl/sysmgr_1.v
@@ -114,9 +114,9 @@ module sysmgr (
 	always @(posedge clk_base)
 		clk_usb_i <= clk_div[0] & ~usb_off;
 
-	// SYS is div-by-4 + gated
+	// SYS is div-by-8 + gated
 	always @(posedge clk_base)
-		clk_sys_i <= clk_div[1] & ~sys_off;
+		clk_sys_i <= clk_div[2] & ~sys_off;
 
 	// LED is div-by-16
 	assign clk_led_i = clk_div[3];
diff --git a/gateware/rtl/sysmgr_2.v b/gateware/rtl/sysmgr_2.v
index c4cb2a6..d14c2b8 100644
--- a/gateware/rtl/sysmgr_2.v
+++ b/gateware/rtl/sysmgr_2.v
@@ -38,7 +38,7 @@ module sysmgr (
 
 	wire      pll_lock;
 
-	reg [2:0] clk_div;
+	reg [1:0] clk_div;
 	reg       clk_sys_i;
 	wire      clk_led_i;
 
@@ -84,7 +84,7 @@ module sysmgr (
 		.DELAY_ADJUSTMENT_MODE_FEEDBACK ("FIXED"),
 		.FDA_FEEDBACK                   (4'b0000),
 		.SHIFTREG_DIV_MODE              (2'b00),
-		.PLLOUT_SELECT_PORTA            ("GENCLK"),
+		.PLLOUT_SELECT_PORTA            ("GENCLK_HALF"),
 		.PLLOUT_SELECT_PORTB            ("GENCLK"),
 		.ENABLE_ICEGATE_PORTA           (1'b0),
 		.ENABLE_ICEGATE_PORTB           (1'b1),
@@ -117,8 +117,8 @@ module sysmgr (
 	always @(posedge clk_base)
 		clk_sys_i <= clk_div[0] & ~sys_off;
 
-	// LED is div-by-8
-	assign clk_led_i = clk_div[2];
+	// LED is div-by-4
+	assign clk_led_i = clk_div[1];
 
 	// Global buffers
 	SB_GB clk_sys_gbuf_I (
diff --git a/gateware/rtl/sysmgr_3.v b/gateware/rtl/sysmgr_3.v
index d1868cb..0458dd2 100644
--- a/gateware/rtl/sysmgr_3.v
+++ b/gateware/rtl/sysmgr_3.v
@@ -37,7 +37,7 @@ module sysmgr (
 
 	wire      pll_lock;
 
-	reg [2:0] clk_div;
+	reg [1:0] clk_div;
 	reg       clk_sys_i;
 	wire      clk_led_i;
 
@@ -60,11 +60,11 @@ module sysmgr (
 
 	// SB_HFOSC
 	// -------
-	// Generates 48 MHz
+	// Generates 24 MHz
 
 	(* ROUTE_THROUGH_FABRIC = 1 *)
 	SB_HFOSC #(
-		.CLKHF_DIV("0b00")
+		.CLKHF_DIV("0b01")
 	) osc_I (
 		.CLKHFPU(1'b1),
 		.CLKHFEN(1'b1),
@@ -87,7 +87,7 @@ module sysmgr (
 		.PLLOUT_SELECT                  ("GENCLK"),
 		.ENABLE_ICEGATE                 (1'b0)
     ) pll_I (
-		.REFERENCECLK    (clk_div[1]),
+		.REFERENCECLK    (clk_div[0]),
 		.PLLOUTCORE      (),
 		.PLLOUTGLOBAL    (clk_usb),
 		.EXTFEEDBACK     (1'b0),
@@ -113,8 +113,8 @@ module sysmgr (
 	always @(posedge clk_base)
 		clk_sys_i <= clk_div[0] & ~sys_off;
 
-	// LED is div-by-8
-	assign clk_led_i = clk_div[2];
+	// LED is div-by-4
+	assign clk_led_i = clk_div[1];
 
 	// Global buffers
 	SB_GB clk_sys_gbuf_I (