From 0aa54bc297c19014dac2c73ebb61ce0eacdd167a Mon Sep 17 00:00:00 2001 From: Sylvain Munaut Date: Mon, 13 Mar 2023 21:45:36 +0100 Subject: [PATCH] hardware/xs-ctrl: Add issues/reworks for VBUS detect Signed-off-by: Sylvain Munaut --- hardware/xs-ctrl/ecn.md | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hardware/xs-ctrl/ecn.md b/hardware/xs-ctrl/ecn.md index db6fd8c..d77d7c3 100644 --- a/hardware/xs-ctrl/ecn.md +++ b/hardware/xs-ctrl/ecn.md @@ -29,6 +29,15 @@ Two of the boards were assembled and tested. * The `CHG_FPGA_n` line through the LED * The `SENSE` line from the voltage divider +* Voltages on the USB lines (most importantly through the pull-up) end + up leaking on the 5V rail through the ESD protection diode, which in + turn causes the `SENSE` line to be triggered ... + + I think ideally the pull-up from the FPGA should actually go through + and external NMOS that enables pull-up from 5V rail. + +* The 5V rail doesn't drain when disconnected. + * The soft-off circuit wouldn't actually turn-off. * When the battery is not connected, the system can't be operated. The @@ -60,6 +69,11 @@ boards. may need an active discharge resistor to make sure the gate discharges when USB is disconnected. Not tested. +* Cut the 5V rail from the ESD diode to prevent voltages on the data line + to leak to an un-powered 5V rail. + +* Added a 1M pulldown on 5V rail so it discharges. + * Replaced C14 with a 2.2uF cap in parallel with a 100k resistor. This makes the `PWR_EN` line only raise to 1.6V which is enough to enable the regulator but makes it easier to discharge without it re-triggering.