mirror of https://gerrit.osmocom.org/simtrace2
205 lines
5.4 KiB
C
205 lines
5.4 KiB
C
/* SIMtrace TC (Timer / Clock) code for ETU tracking
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*
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* (C) 2006-2016 by Harald Welte <laforge@gnumonks.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include "utils.h"
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#include "tc_etu.h"
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#include "chip.h"
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/* pins for Channel 0 of TC-block 0, we only use TCLK + TIOB */
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#define PIN_TCLK0 {PIO_PA4, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT }
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#define PIN_TIOA0 {PIO_PA0, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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#define PIN_TIOB0 {PIO_PA1, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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static const Pin pins_tc0[] = { PIN_TCLK0, PIN_TIOB0 };
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/* pins for Channel 2 of TC-block 0, we only use TCLK + TIOB */
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#define PIN_TCLK2 {PIO_PA29, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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#define PIN_TIOA2 {PIO_PA26, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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#define PIN_TIOB2 {PIO_PA27, PIOA, ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
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static const Pin pins_tc2[] = { PIN_TCLK2, PIN_TIOB2 };
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struct tc_etu_state {
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/* total negotiated waiting time (default = 9600) */
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uint16_t waiting_time;
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/* how many clock cycles per ETU (default = 372) */
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uint16_t clocks_per_etu;
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/* how many ETUs does waiting time correspond ? */
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uint16_t wait_events;
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/* how many ETUs have we seen expire so far? */
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uint16_t nr_events;
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/* channel number */
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uint8_t chan_nr;
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/* Timer/Counter register pointer */
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TcChannel *chan;
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/* User reference */
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void *handle;
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};
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#define INIT_TE_STATE(n) { \
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.waiting_time = 9600, \
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.clocks_per_etu = 372, \
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.wait_events = 10, \
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.nr_events = 0, \
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.chan_nr = n, \
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}
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static struct tc_etu_state te_state0 = INIT_TE_STATE(0);
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static struct tc_etu_state te_state2 = INIT_TE_STATE(2);
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static struct tc_etu_state *get_te(uint8_t chan_nr)
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{
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if (chan_nr == 0)
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return &te_state0;
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else
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return &te_state2;
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}
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static void tc_etu_irq(struct tc_etu_state *te)
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{
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uint32_t sr = te->chan->TC_SR;
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if (sr & TC_SR_ETRGS) {
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/* external trigger, i.e. we have seen a bit on I/O */
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te->nr_events = 0;
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}
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if (sr & TC_SR_CPCS) {
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/* Compare C event has occurred, i.e. 1 ETU expired */
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te->nr_events++;
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if (te->nr_events == te->wait_events/2) {
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/* Indicate that half the waiting tim has expired */
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tc_etu_wtime_half_expired(te->handle);
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}
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if (te->nr_events >= te->wait_events) {
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TcChannel *chan = te->chan;
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chan->TC_CMR |= TC_CMR_ENETRG;
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/* disable and re-enable clock to make it stop */
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chan->TC_CCR = TC_CCR_CLKDIS;
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chan->TC_CCR = TC_CCR_CLKEN;
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/* Indicate that the waiting tim has expired */
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tc_etu_wtime_expired(te->handle);
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}
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}
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}
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void TC0_IrqHandler(void)
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{
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tc_etu_irq(&te_state0);
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}
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void TC2_IrqHandler(void)
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{
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tc_etu_irq(&te_state2);
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}
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static void recalc_nr_events(struct tc_etu_state *te)
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{
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te->wait_events = te->waiting_time / 12;
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te->chan->TC_RC = te->clocks_per_etu * 12;
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}
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void tc_etu_set_wtime(uint8_t chan_nr, uint16_t wtime)
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{
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struct tc_etu_state *te = get_te(chan_nr);
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te->waiting_time = wtime;
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recalc_nr_events(te);
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}
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void tc_etu_set_etu(uint8_t chan_nr, uint16_t etu)
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{
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struct tc_etu_state *te = get_te(chan_nr);
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te->clocks_per_etu = etu;
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recalc_nr_events(te);
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}
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void tc_etu_enable(uint8_t chan_nr)
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{
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struct tc_etu_state *te = get_te(chan_nr);
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te->nr_events = 0;
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te->chan->TC_CCR = TC_CCR_CLKEN|TC_CCR_SWTRG;
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}
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void tc_etu_disable(uint8_t chan_nr)
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{
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struct tc_etu_state *te = get_te(chan_nr);
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te->nr_events = 0;
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te->chan->TC_CCR = TC_CCR_CLKDIS;
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}
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void tc_etu_init(uint8_t chan_nr, void *handle)
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{
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struct tc_etu_state *te = get_te(chan_nr);
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uint32_t tc_clks;
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te->handle = handle;
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switch (chan_nr) {
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case 0:
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/* Configure PA4(TCLK0), PA1(TIB0) */
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PIO_Configure(pins_tc0, ARRAY_SIZE(pins_tc0));
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PMC_EnablePeripheral(ID_TC0);
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/* route TCLK0 to XC2 */
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TC0->TC_BMR &= ~TC_BMR_TC0XC0S_Msk;
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TC0->TC_BMR |= TC_BMR_TC0XC0S_TCLK0;
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tc_clks = TC_CMR_TCCLKS_XC0;
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/* register interrupt handler */
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NVIC_EnableIRQ(TC0_IRQn);
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te->chan = &TC0->TC_CHANNEL[0];
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break;
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case 2:
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/* Configure PA29(TCLK2), PA27(TIOB2) */
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PIO_Configure(pins_tc2, ARRAY_SIZE(pins_tc2));
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PMC_EnablePeripheral(ID_TC2);
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/* route TCLK2 to XC2. TC0 really means TCA in this case */
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TC0->TC_BMR &= ~TC_BMR_TC2XC2S_Msk;
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TC0->TC_BMR |= TC_BMR_TC2XC2S_TCLK2;
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tc_clks = TC_CMR_TCCLKS_XC2;
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/* register interrupt handler */
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NVIC_EnableIRQ(TC2_IRQn);
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te->chan = &TC0->TC_CHANNEL[2];
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break;
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default:
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return;
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}
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/* enable interrupts for Compare-C and external trigger */
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te->chan->TC_IER = TC_IER_CPCS | TC_IER_ETRGS;
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te->chan->TC_CMR = tc_clks | /* XC(TCLK) clock */
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TC_CMR_WAVE | /* wave mode */
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TC_CMR_ETRGEDG_FALLING | /* ext trig on falling edge */
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TC_CMR_EEVT_TIOB | /* ext trig is TIOB0 */
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TC_CMR_ENETRG | /* enable ext trig */
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TC_CMR_WAVSEL_UP_RC | /* wave mode up */
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TC_CMR_ACPA_SET | /* set TIOA on a compare */
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TC_CMR_ACPC_CLEAR | /* clear TIOA on C compare */
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TC_CMR_ASWTRG_CLEAR; /* Clear TIOA on sw trig */
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tc_etu_set_etu(chan_nr, 372);
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/* start with a disabled clock */
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tc_etu_disable(chan_nr);
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/* Reset to start timers */
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TC0->TC_BCR = TC_BCR_SYNC;
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}
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