mirror of https://gerrit.osmocom.org/simtrace2
clk calculation: updated max mul val
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16
clk_calc.py
16
clk_calc.py
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@ -1,6 +1,9 @@
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# frequ in MHz
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# frequ in MHz
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f=18.432
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f=18.432
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ftarg=64.0
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# Master clock:
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#ftarg=64.0
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# USB Clock:
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ftarg=48.0
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# PLL range: 60 MHz <= PLL <= 130 MHz
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# PLL range: 60 MHz <= PLL <= 130 MHz
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# MUL range: 4 <= MUL <= 7
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# MUL range: 4 <= MUL <= 7
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@ -8,10 +11,13 @@ ftarg=64.0
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min_err_val=[1.0, 0.0]
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min_err_val=[1.0, 0.0]
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min_err=f
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min_err=f
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for mul in range(1, 8):
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#for mul in range(1, 8):
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for div in range(1, 0x20):
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for mul in range(1, 36):
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err=abs((f*mul/(1.0*div)) - ftarg)
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#for div in range(1, 0x20):
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print(mul, div, err)
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for div in range(1, 255):
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freq=(f*mul/(1.0*div))
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err=abs(freq - ftarg)
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print(mul, div, freq, err)
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if(err < min_err):
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if(err < min_err):
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min_err_val=[mul, div]
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min_err_val=[mul, div]
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print("last minerr: %f, new minerr: %f, mul: %d, div: %d" % (min_err, err, mul, div))
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print("last minerr: %f, new minerr: %f, mul: %d, div: %d" % (min_err, err, mul, div))
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