schematic: make it more readable

- VCC is up
- GND is down
- group the parts by functionality and use net name
- separate decoupling capacitors
- arrange groups from left input to right output

Change-Id: I2d894dd10b8b619ccbce1ae8b7e25316963157c8
This commit is contained in:
Kevin Redon 2019-09-03 14:48:10 +02:00
parent 9bf63354e7
commit 7fc392aabf
4 changed files with 1858 additions and 1972 deletions

View File

@ -613,6 +613,21 @@ X pwr 1 0 0 0 U 50 50 0 0 w
ENDDRAW
ENDDEF
#
# power_VBUS
#
DEF power_VBUS #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_VBUS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VBUS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# smartcard_ISO7816_NO
#
DEF smartcard_ISO7816_NO P 0 40 Y Y 2 F N

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@ -1,4 +1,4 @@
update=Di 27 Aug 2019 16:29:29 CEST
update=Di 03 Sep 2019 14:46:50 CEST
last_client=kicad
[general]
version=1
@ -44,3 +44,13 @@ EquName1=devcms
[eeschema]
version=1
LibDir=
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=../pcb/schema/
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1

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