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Andre Przywara d9f4bb27db target-i386: add SSE4a instruction support ... This adds support for the AMD Phenom/Barcelona's SSE4a instructions. Those include insertq and extrq, which are doing shift and mask on XMM registers, in two versions (immediate shift/length values and stored in another XMM register). Additionally it implements movntss, movntsd, which are scalar non-temporal stores (avoiding cache trashing). These are implemented as normal stores, though. SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2009-10-04 14:09:41 +02:00
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TODO	Unbreak large mem support by removing kqemu	2009-08-24 08:02:55 -05:00
cpu.h	cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal	2009-08-24 08:21:42 -05:00
exec.h	Work around OpenSolaris sys/regset.h namespace pollution	2009-09-12 12:36:11 +00:00
helper.c	Revert "Get rid of _t suffix"	2009-10-01 16:12:16 -05:00
helper.h	x86: Add support for resume flag	2009-05-22 10:50:37 -05:00
helper_template.h	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
kvm.c	gcc wants 1st static and then const	2009-09-25 19:52:06 +00:00
machine.c	kvm: Simplify cpu_synchronize_state()	2009-08-27 20:35:30 -05:00
op_helper.c	Revert "Get rid of _t suffix"	2009-10-01 16:12:16 -05:00
ops_sse.h	target-i386: add SSE4a instruction support	2009-10-04 14:09:41 +02:00
ops_sse_header.h	target-i386: add SSE4a instruction support	2009-10-04 14:09:41 +02:00
svm.h	reworked SVM interrupt handling logic - fixed vmrun EIP saved value - reworked cr8 handling - added CPUState.hflags2	2008-06-04 17:02:19 +00:00
translate.c	target-i386: add SSE4a instruction support	2009-10-04 14:09:41 +02:00