758 lines
20 KiB
C
758 lines
20 KiB
C
/*
|
|
* Xtensa ISA:
|
|
* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
|
|
*
|
|
* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are met:
|
|
* * Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
|
|
* * Neither the name of the Open Source and Linux Lab nor the
|
|
* names of its contributors may be used to endorse or promote products
|
|
* derived from this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
|
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
|
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
|
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
|
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
|
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
|
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#include <stdio.h>
|
|
|
|
#include "cpu.h"
|
|
#include "exec-all.h"
|
|
#include "disas.h"
|
|
#include "tcg-op.h"
|
|
#include "qemu-log.h"
|
|
|
|
#include "helpers.h"
|
|
#define GEN_HELPER 1
|
|
#include "helpers.h"
|
|
|
|
typedef struct DisasContext {
|
|
const XtensaConfig *config;
|
|
TranslationBlock *tb;
|
|
uint32_t pc;
|
|
uint32_t next_pc;
|
|
int is_jmp;
|
|
int singlestep_enabled;
|
|
} DisasContext;
|
|
|
|
static TCGv_ptr cpu_env;
|
|
static TCGv_i32 cpu_pc;
|
|
static TCGv_i32 cpu_R[16];
|
|
|
|
#include "gen-icount.h"
|
|
|
|
void xtensa_translate_init(void)
|
|
{
|
|
static const char * const regnames[] = {
|
|
"ar0", "ar1", "ar2", "ar3",
|
|
"ar4", "ar5", "ar6", "ar7",
|
|
"ar8", "ar9", "ar10", "ar11",
|
|
"ar12", "ar13", "ar14", "ar15",
|
|
};
|
|
int i;
|
|
|
|
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
|
|
cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
|
|
offsetof(CPUState, pc), "pc");
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
|
|
offsetof(CPUState, regs[i]),
|
|
regnames[i]);
|
|
}
|
|
#define GEN_HELPER 2
|
|
#include "helpers.h"
|
|
}
|
|
|
|
static inline bool option_enabled(DisasContext *dc, int opt)
|
|
{
|
|
return xtensa_option_enabled(dc->config, opt);
|
|
}
|
|
|
|
static void gen_exception(int excp)
|
|
{
|
|
TCGv_i32 tmp = tcg_const_i32(excp);
|
|
gen_helper_exception(tmp);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
|
|
static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
|
|
{
|
|
tcg_gen_mov_i32(cpu_pc, dest);
|
|
if (dc->singlestep_enabled) {
|
|
gen_exception(EXCP_DEBUG);
|
|
} else {
|
|
if (slot >= 0) {
|
|
tcg_gen_goto_tb(slot);
|
|
tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
|
|
} else {
|
|
tcg_gen_exit_tb(0);
|
|
}
|
|
}
|
|
dc->is_jmp = DISAS_UPDATE;
|
|
}
|
|
|
|
static void gen_jump(DisasContext *dc, TCGv dest)
|
|
{
|
|
gen_jump_slot(dc, dest, -1);
|
|
}
|
|
|
|
static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
|
|
{
|
|
TCGv_i32 tmp = tcg_const_i32(dest);
|
|
if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
|
|
slot = -1;
|
|
}
|
|
gen_jump_slot(dc, tmp, slot);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
|
|
static void gen_brcond(DisasContext *dc, TCGCond cond,
|
|
TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
|
|
{
|
|
int label = gen_new_label();
|
|
|
|
tcg_gen_brcond_i32(cond, t0, t1, label);
|
|
gen_jumpi(dc, dc->next_pc, 0);
|
|
gen_set_label(label);
|
|
gen_jumpi(dc, dc->pc + offset, 1);
|
|
}
|
|
|
|
static void gen_brcondi(DisasContext *dc, TCGCond cond,
|
|
TCGv_i32 t0, uint32_t t1, uint32_t offset)
|
|
{
|
|
TCGv_i32 tmp = tcg_const_i32(t1);
|
|
gen_brcond(dc, cond, t0, tmp, offset);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
|
|
static void disas_xtensa_insn(DisasContext *dc)
|
|
{
|
|
#define HAS_OPTION(opt) do { \
|
|
if (!option_enabled(dc, opt)) { \
|
|
qemu_log("Option %d is not enabled %s:%d\n", \
|
|
(opt), __FILE__, __LINE__); \
|
|
goto invalid_opcode; \
|
|
} \
|
|
} while (0)
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
#define OP0 (((b0) & 0xf0) >> 4)
|
|
#define OP1 (((b2) & 0xf0) >> 4)
|
|
#define OP2 ((b2) & 0xf)
|
|
#define RRR_R ((b1) & 0xf)
|
|
#define RRR_S (((b1) & 0xf0) >> 4)
|
|
#define RRR_T ((b0) & 0xf)
|
|
#else
|
|
#define OP0 (((b0) & 0xf))
|
|
#define OP1 (((b2) & 0xf))
|
|
#define OP2 (((b2) & 0xf0) >> 4)
|
|
#define RRR_R (((b1) & 0xf0) >> 4)
|
|
#define RRR_S (((b1) & 0xf))
|
|
#define RRR_T (((b0) & 0xf0) >> 4)
|
|
#endif
|
|
|
|
#define RRRN_R RRR_R
|
|
#define RRRN_S RRR_S
|
|
#define RRRN_T RRR_T
|
|
|
|
#define RRI8_R RRR_R
|
|
#define RRI8_S RRR_S
|
|
#define RRI8_T RRR_T
|
|
#define RRI8_IMM8 (b2)
|
|
#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
#define RI16_IMM16 (((b1) << 8) | (b2))
|
|
#else
|
|
#define RI16_IMM16 (((b2) << 8) | (b1))
|
|
#endif
|
|
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
#define CALL_N (((b0) & 0xc) >> 2)
|
|
#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
|
|
#else
|
|
#define CALL_N (((b0) & 0x30) >> 4)
|
|
#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
|
|
#endif
|
|
#define CALL_OFFSET_SE \
|
|
(((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
|
|
|
|
#define CALLX_N CALL_N
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
#define CALLX_M ((b0) & 0x3)
|
|
#else
|
|
#define CALLX_M (((b0) & 0xc0) >> 6)
|
|
#endif
|
|
#define CALLX_S RRR_S
|
|
|
|
#define BRI12_M CALLX_M
|
|
#define BRI12_S RRR_S
|
|
#ifdef TARGET_WORDS_BIGENDIAN
|
|
#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
|
|
#else
|
|
#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
|
|
#endif
|
|
#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
|
|
|
|
#define BRI8_M BRI12_M
|
|
#define BRI8_R RRI8_R
|
|
#define BRI8_S RRI8_S
|
|
#define BRI8_IMM8 RRI8_IMM8
|
|
#define BRI8_IMM8_SE RRI8_IMM8_SE
|
|
|
|
#define RSR_SR (b1)
|
|
|
|
uint8_t b0 = ldub_code(dc->pc);
|
|
uint8_t b1 = ldub_code(dc->pc + 1);
|
|
uint8_t b2 = ldub_code(dc->pc + 2);
|
|
|
|
static const uint32_t B4CONST[] = {
|
|
0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
|
|
};
|
|
|
|
static const uint32_t B4CONSTU[] = {
|
|
32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
|
|
};
|
|
|
|
if (OP0 >= 8) {
|
|
dc->next_pc = dc->pc + 2;
|
|
HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
|
|
} else {
|
|
dc->next_pc = dc->pc + 3;
|
|
}
|
|
|
|
switch (OP0) {
|
|
case 0: /*QRST*/
|
|
switch (OP1) {
|
|
case 0: /*RST0*/
|
|
switch (OP2) {
|
|
case 0: /*ST0*/
|
|
if ((RRR_R & 0xc) == 0x8) {
|
|
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
|
|
}
|
|
|
|
switch (RRR_R) {
|
|
case 0: /*SNM0*/
|
|
break;
|
|
|
|
case 1: /*MOVSPw*/
|
|
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
|
break;
|
|
|
|
case 2: /*SYNC*/
|
|
break;
|
|
|
|
case 3:
|
|
break;
|
|
|
|
}
|
|
break;
|
|
|
|
case 1: /*AND*/
|
|
tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 2: /*OR*/
|
|
tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 3: /*XOR*/
|
|
tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 4: /*ST1*/
|
|
break;
|
|
|
|
case 5: /*TLB*/
|
|
break;
|
|
|
|
case 6: /*RT0*/
|
|
switch (RRR_S) {
|
|
case 0: /*NEG*/
|
|
tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 1: /*ABS*/
|
|
{
|
|
int label = gen_new_label();
|
|
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
|
|
tcg_gen_brcondi_i32(
|
|
TCG_COND_GE, cpu_R[RRR_R], 0, label);
|
|
tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
|
|
gen_set_label(label);
|
|
}
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 7: /*reserved*/
|
|
break;
|
|
|
|
case 8: /*ADD*/
|
|
tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 9: /*ADD**/
|
|
case 10:
|
|
case 11:
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
|
|
tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 12: /*SUB*/
|
|
tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
|
|
break;
|
|
|
|
case 13: /*SUB**/
|
|
case 14:
|
|
case 15:
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
|
|
tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 1: /*RST1*/
|
|
break;
|
|
|
|
case 2: /*RST2*/
|
|
break;
|
|
|
|
case 3: /*RST3*/
|
|
break;
|
|
|
|
case 4: /*EXTUI*/
|
|
case 5:
|
|
break;
|
|
|
|
case 6: /*CUST0*/
|
|
break;
|
|
|
|
case 7: /*CUST1*/
|
|
break;
|
|
|
|
case 8: /*LSCXp*/
|
|
HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
|
|
break;
|
|
|
|
case 9: /*LSC4*/
|
|
break;
|
|
|
|
case 10: /*FP0*/
|
|
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
|
|
break;
|
|
|
|
case 11: /*FP1*/
|
|
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 1: /*L32R*/
|
|
{
|
|
TCGv_i32 tmp = tcg_const_i32(
|
|
(0xfffc0000 | (RI16_IMM16 << 2)) +
|
|
((dc->pc + 3) & ~3));
|
|
|
|
/* no ext L32R */
|
|
|
|
tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 2: /*LSAI*/
|
|
break;
|
|
|
|
case 3: /*LSCIp*/
|
|
HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
|
|
break;
|
|
|
|
case 4: /*MAC16d*/
|
|
HAS_OPTION(XTENSA_OPTION_MAC16);
|
|
break;
|
|
|
|
case 5: /*CALLN*/
|
|
switch (CALL_N) {
|
|
case 0: /*CALL0*/
|
|
tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
|
|
gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
|
|
break;
|
|
|
|
case 1: /*CALL4w*/
|
|
case 2: /*CALL8w*/
|
|
case 3: /*CALL12w*/
|
|
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case 6: /*SI*/
|
|
switch (CALL_N) {
|
|
case 0: /*J*/
|
|
gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
|
|
break;
|
|
|
|
case 1: /*BZ*/
|
|
{
|
|
static const TCGCond cond[] = {
|
|
TCG_COND_EQ, /*BEQZ*/
|
|
TCG_COND_NE, /*BNEZ*/
|
|
TCG_COND_LT, /*BLTZ*/
|
|
TCG_COND_GE, /*BGEZ*/
|
|
};
|
|
|
|
gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
|
|
4 + BRI12_IMM12_SE);
|
|
}
|
|
break;
|
|
|
|
case 2: /*BI0*/
|
|
{
|
|
static const TCGCond cond[] = {
|
|
TCG_COND_EQ, /*BEQI*/
|
|
TCG_COND_NE, /*BNEI*/
|
|
TCG_COND_LT, /*BLTI*/
|
|
TCG_COND_GE, /*BGEI*/
|
|
};
|
|
|
|
gen_brcondi(dc, cond[BRI8_M & 3],
|
|
cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
|
|
}
|
|
break;
|
|
|
|
case 3: /*BI1*/
|
|
switch (BRI8_M) {
|
|
case 0: /*ENTRYw*/
|
|
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
|
|
break;
|
|
|
|
case 1: /*B1*/
|
|
switch (BRI8_R) {
|
|
case 0: /*BFp*/
|
|
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
|
|
break;
|
|
|
|
case 1: /*BTp*/
|
|
HAS_OPTION(XTENSA_OPTION_BOOLEAN);
|
|
break;
|
|
|
|
case 8: /*LOOP*/
|
|
break;
|
|
|
|
case 9: /*LOOPNEZ*/
|
|
break;
|
|
|
|
case 10: /*LOOPGTZ*/
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
|
|
}
|
|
break;
|
|
|
|
case 2: /*BLTUI*/
|
|
case 3: /*BGEUI*/
|
|
gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
|
|
cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
|
|
break;
|
|
}
|
|
break;
|
|
|
|
}
|
|
break;
|
|
|
|
case 7: /*B*/
|
|
{
|
|
TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
|
|
|
|
switch (RRI8_R & 7) {
|
|
case 0: /*BNONE*/ /*BANY*/
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 1: /*BEQ*/ /*BNE*/
|
|
case 2: /*BLT*/ /*BGE*/
|
|
case 3: /*BLTU*/ /*BGEU*/
|
|
{
|
|
static const TCGCond cond[] = {
|
|
[1] = TCG_COND_EQ,
|
|
[2] = TCG_COND_LT,
|
|
[3] = TCG_COND_LTU,
|
|
[9] = TCG_COND_NE,
|
|
[10] = TCG_COND_GE,
|
|
[11] = TCG_COND_GEU,
|
|
};
|
|
gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
|
|
4 + RRI8_IMM8_SE);
|
|
}
|
|
break;
|
|
|
|
case 4: /*BALL*/ /*BNALL*/
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
|
|
gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
|
|
4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 5: /*BBC*/ /*BBS*/
|
|
{
|
|
TCGv_i32 bit = tcg_const_i32(1);
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
|
|
tcg_gen_shl_i32(bit, bit, tmp);
|
|
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
tcg_temp_free(bit);
|
|
}
|
|
break;
|
|
|
|
case 6: /*BBCI*/ /*BBSI*/
|
|
case 7:
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
|
|
1 << (((RRI8_R & 1) << 4) | RRI8_T));
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
}
|
|
}
|
|
break;
|
|
|
|
#define gen_narrow_load_store(type) do { \
|
|
TCGv_i32 addr = tcg_temp_new_i32(); \
|
|
tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
|
|
tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
|
|
tcg_temp_free(addr); \
|
|
} while (0)
|
|
|
|
case 8: /*L32I.Nn*/
|
|
gen_narrow_load_store(ld32u);
|
|
break;
|
|
|
|
case 9: /*S32I.Nn*/
|
|
gen_narrow_load_store(st32);
|
|
break;
|
|
#undef gen_narrow_load_store
|
|
|
|
case 10: /*ADD.Nn*/
|
|
tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
|
|
break;
|
|
|
|
case 11: /*ADDI.Nn*/
|
|
tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
|
|
break;
|
|
|
|
case 12: /*ST2n*/
|
|
if (RRRN_T < 8) { /*MOVI.Nn*/
|
|
tcg_gen_movi_i32(cpu_R[RRRN_S],
|
|
RRRN_R | (RRRN_T << 4) |
|
|
((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
|
|
} else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
|
|
TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
|
|
|
|
gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
|
|
4 + (RRRN_R | ((RRRN_T & 3) << 4)));
|
|
}
|
|
break;
|
|
|
|
case 13: /*ST3n*/
|
|
switch (RRRN_R) {
|
|
case 0: /*MOV.Nn*/
|
|
tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
|
|
break;
|
|
|
|
case 15: /*S3*/
|
|
switch (RRRN_T) {
|
|
case 0: /*RET.Nn*/
|
|
gen_jump(dc, cpu_R[0]);
|
|
break;
|
|
|
|
case 1: /*RETW.Nn*/
|
|
break;
|
|
|
|
case 2: /*BREAK.Nn*/
|
|
break;
|
|
|
|
case 3: /*NOP.Nn*/
|
|
break;
|
|
|
|
case 6: /*ILL.Nn*/
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
|
|
dc->pc = dc->next_pc;
|
|
return;
|
|
|
|
invalid_opcode:
|
|
qemu_log("INVALID(pc = %08x)\n", dc->pc);
|
|
dc->pc = dc->next_pc;
|
|
#undef HAS_OPTION
|
|
}
|
|
|
|
static void check_breakpoint(CPUState *env, DisasContext *dc)
|
|
{
|
|
CPUBreakpoint *bp;
|
|
|
|
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
|
if (bp->pc == dc->pc) {
|
|
tcg_gen_movi_i32(cpu_pc, dc->pc);
|
|
gen_exception(EXCP_DEBUG);
|
|
dc->is_jmp = DISAS_UPDATE;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void gen_intermediate_code_internal(
|
|
CPUState *env, TranslationBlock *tb, int search_pc)
|
|
{
|
|
DisasContext dc;
|
|
int insn_count = 0;
|
|
int j, lj = -1;
|
|
uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
|
|
int max_insns = tb->cflags & CF_COUNT_MASK;
|
|
uint32_t pc_start = tb->pc;
|
|
uint32_t next_page_start =
|
|
(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
|
|
|
if (max_insns == 0) {
|
|
max_insns = CF_COUNT_MASK;
|
|
}
|
|
|
|
dc.config = env->config;
|
|
dc.singlestep_enabled = env->singlestep_enabled;
|
|
dc.tb = tb;
|
|
dc.pc = pc_start;
|
|
dc.is_jmp = DISAS_NEXT;
|
|
|
|
gen_icount_start();
|
|
|
|
do {
|
|
check_breakpoint(env, &dc);
|
|
|
|
if (search_pc) {
|
|
j = gen_opc_ptr - gen_opc_buf;
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j) {
|
|
gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
}
|
|
gen_opc_pc[lj] = dc.pc;
|
|
gen_opc_instr_start[lj] = 1;
|
|
gen_opc_icount[lj] = insn_count;
|
|
}
|
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
|
tcg_gen_debug_insn_start(dc.pc);
|
|
}
|
|
|
|
disas_xtensa_insn(&dc);
|
|
++insn_count;
|
|
if (env->singlestep_enabled) {
|
|
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
|
gen_exception(EXCP_DEBUG);
|
|
break;
|
|
}
|
|
} while (dc.is_jmp == DISAS_NEXT &&
|
|
insn_count < max_insns &&
|
|
dc.pc < next_page_start &&
|
|
gen_opc_ptr < gen_opc_end);
|
|
|
|
if (dc.is_jmp == DISAS_NEXT) {
|
|
gen_jumpi(&dc, dc.pc, 0);
|
|
}
|
|
gen_icount_end(tb, insn_count);
|
|
*gen_opc_ptr = INDEX_op_end;
|
|
|
|
if (!search_pc) {
|
|
tb->size = dc.pc - pc_start;
|
|
tb->icount = insn_count;
|
|
}
|
|
}
|
|
|
|
void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(env, tb, 0);
|
|
}
|
|
|
|
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(env, tb, 1);
|
|
}
|
|
|
|
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
|
int flags)
|
|
{
|
|
int i;
|
|
|
|
cpu_fprintf(f, "PC=%08x\n", env->pc);
|
|
|
|
for (i = 0; i < 16; ++i) {
|
|
cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
|
|
(i % 4) == 3 ? '\n' : ' ');
|
|
}
|
|
}
|
|
|
|
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
|
|
{
|
|
env->pc = gen_opc_pc[pc_pos];
|
|
}
|