287 lines
7.4 KiB
C
287 lines
7.4 KiB
C
/*
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* ARM MPCore internal peripheral emulation (common code).
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*
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* Copyright (c) 2006-2007 CodeSourcery.
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* Written by Paul Brook
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*
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* This code is licensed under the GPL.
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*/
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#include "sysbus.h"
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#include "qemu-timer.h"
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#define NCPU 4
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static inline int
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gic_get_current_cpu(void)
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{
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return cpu_single_env->cpu_index;
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}
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#include "arm_gic.c"
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/* MPCore private memory region. */
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typedef struct {
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uint32_t count;
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uint32_t load;
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uint32_t control;
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uint32_t status;
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uint32_t old_status;
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int64_t tick;
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QEMUTimer *timer;
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struct mpcore_priv_state *mpcore;
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int id; /* Encodes both timer/watchdog and CPU. */
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} mpcore_timer_state;
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typedef struct mpcore_priv_state {
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gic_state gic;
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uint32_t scu_control;
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int iomemtype;
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mpcore_timer_state timer[8];
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uint32_t num_cpu;
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} mpcore_priv_state;
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/* Per-CPU Timers. */
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static inline void mpcore_timer_update_irq(mpcore_timer_state *s)
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{
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if (s->status & ~s->old_status) {
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gic_set_pending_private(&s->mpcore->gic, s->id >> 1, 29 + (s->id & 1));
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}
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s->old_status = s->status;
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}
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/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
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static inline uint32_t mpcore_timer_scale(mpcore_timer_state *s)
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{
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return (((s->control >> 8) & 0xff) + 1) * 10;
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}
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static void mpcore_timer_reload(mpcore_timer_state *s, int restart)
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{
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if (s->count == 0)
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return;
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if (restart)
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s->tick = qemu_get_clock_ns(vm_clock);
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s->tick += (int64_t)s->count * mpcore_timer_scale(s);
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qemu_mod_timer(s->timer, s->tick);
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}
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static void mpcore_timer_tick(void *opaque)
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{
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mpcore_timer_state *s = (mpcore_timer_state *)opaque;
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s->status = 1;
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if (s->control & 2) {
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s->count = s->load;
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mpcore_timer_reload(s, 0);
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} else {
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s->count = 0;
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}
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mpcore_timer_update_irq(s);
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}
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static uint32_t mpcore_timer_read(mpcore_timer_state *s, int offset)
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{
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int64_t val;
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switch (offset) {
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case 0: /* Load */
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return s->load;
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/* Fall through. */
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case 4: /* Counter. */
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if (((s->control & 1) == 0) || (s->count == 0))
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return 0;
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/* Slow and ugly, but hopefully won't happen too often. */
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val = s->tick - qemu_get_clock_ns(vm_clock);
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val /= mpcore_timer_scale(s);
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if (val < 0)
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val = 0;
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return val;
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case 8: /* Control. */
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return s->control;
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case 12: /* Interrupt status. */
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return s->status;
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default:
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return 0;
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}
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}
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static void mpcore_timer_write(mpcore_timer_state *s, int offset,
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uint32_t value)
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{
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int64_t old;
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switch (offset) {
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case 0: /* Load */
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s->load = value;
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/* Fall through. */
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case 4: /* Counter. */
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if ((s->control & 1) && s->count) {
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/* Cancel the previous timer. */
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qemu_del_timer(s->timer);
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}
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s->count = value;
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if (s->control & 1) {
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mpcore_timer_reload(s, 1);
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}
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break;
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case 8: /* Control. */
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old = s->control;
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s->control = value;
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if (((old & 1) == 0) && (value & 1)) {
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if (s->count == 0 && (s->control & 2))
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s->count = s->load;
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mpcore_timer_reload(s, 1);
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}
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break;
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case 12: /* Interrupt status. */
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s->status &= ~value;
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mpcore_timer_update_irq(s);
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break;
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}
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}
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static void mpcore_timer_init(mpcore_priv_state *mpcore,
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mpcore_timer_state *s, int id)
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{
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s->id = id;
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s->mpcore = mpcore;
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s->timer = qemu_new_timer_ns(vm_clock, mpcore_timer_tick, s);
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}
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/* Per-CPU private memory mapped IO. */
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static uint32_t mpcore_priv_read(void *opaque, target_phys_addr_t offset)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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int id;
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offset &= 0xfff;
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if (offset < 0x100) {
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/* SCU */
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switch (offset) {
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case 0x00: /* Control. */
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return s->scu_control;
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case 0x04: /* Configuration. */
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id = ((1 << s->num_cpu) - 1) << 4;
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return id | (s->num_cpu - 1);
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case 0x08: /* CPU status. */
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return 0;
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case 0x0c: /* Invalidate all. */
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return 0;
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default:
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goto bad_reg;
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}
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} else if (offset < 0x600) {
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/* Interrupt controller. */
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if (offset < 0x200) {
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x200) >> 8;
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if (id >= s->num_cpu) {
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return 0;
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}
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}
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return gic_cpu_read(&s->gic, id, offset & 0xff);
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} else if (offset < 0xb00) {
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/* Timers. */
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if (offset < 0x700) {
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x700) >> 8;
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if (id >= s->num_cpu) {
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return 0;
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}
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}
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id <<= 1;
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if (offset & 0x20)
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id++;
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return mpcore_timer_read(&s->timer[id], offset & 0xf);
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}
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bad_reg:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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return 0;
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}
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static void mpcore_priv_write(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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{
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mpcore_priv_state *s = (mpcore_priv_state *)opaque;
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int id;
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offset &= 0xfff;
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if (offset < 0x100) {
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/* SCU */
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switch (offset) {
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case 0: /* Control register. */
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s->scu_control = value & 1;
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break;
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case 0x0c: /* Invalidate all. */
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/* This is a no-op as cache is not emulated. */
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break;
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default:
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goto bad_reg;
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}
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} else if (offset < 0x600) {
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/* Interrupt controller. */
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if (offset < 0x200) {
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x200) >> 8;
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}
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if (id < s->num_cpu) {
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gic_cpu_write(&s->gic, id, offset & 0xff, value);
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}
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} else if (offset < 0xb00) {
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/* Timers. */
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if (offset < 0x700) {
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id = gic_get_current_cpu();
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} else {
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id = (offset - 0x700) >> 8;
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}
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if (id < s->num_cpu) {
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id <<= 1;
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if (offset & 0x20)
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id++;
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mpcore_timer_write(&s->timer[id], offset & 0xf, value);
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}
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return;
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}
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return;
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bad_reg:
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hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset);
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}
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static CPUReadMemoryFunc * const mpcore_priv_readfn[] = {
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mpcore_priv_read,
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mpcore_priv_read,
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mpcore_priv_read
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};
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static CPUWriteMemoryFunc * const mpcore_priv_writefn[] = {
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mpcore_priv_write,
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mpcore_priv_write,
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mpcore_priv_write
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};
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static void mpcore_priv_map(SysBusDevice *dev, target_phys_addr_t base)
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{
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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cpu_register_physical_memory(base, 0x1000, s->iomemtype);
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cpu_register_physical_memory(base + 0x1000, 0x1000, s->gic.iomemtype);
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}
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static int mpcore_priv_init(SysBusDevice *dev)
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{
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mpcore_priv_state *s = FROM_SYSBUSGIC(mpcore_priv_state, dev);
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int i;
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gic_init(&s->gic, s->num_cpu);
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s->iomemtype = cpu_register_io_memory(mpcore_priv_readfn,
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mpcore_priv_writefn, s,
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DEVICE_NATIVE_ENDIAN);
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sysbus_init_mmio_cb(dev, 0x2000, mpcore_priv_map);
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for (i = 0; i < s->num_cpu * 2; i++) {
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mpcore_timer_init(s, &s->timer[i], i);
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}
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return 0;
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}
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