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Peter Maydell ca27c052d9 target-arm: Implement a minimal set of cp14 debug registers ... Newer ARM kernels try to probe for whether the CPU has hardware breakpoint support. For this to work QEMU has to implement a minimal set of the cp14 debug registers. The architecture requires v7 cores to implement debug and so there is no defined way to report its absence; however in practice returning a zero DBGDIDR (ie with a reserved value for "debug architecture version") should cause well-written hw debug users to do the right thing. We also implement DBGDRAR and DBGDSAR as RAZ, indicating no memory mapped debug components. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>		2011-03-07 09:46:19 +01:00
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cpu.h	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
exec.h	move cpu_pc_from_tb to target-*/exec.h	2010-07-03 09:48:12 +03:00
helper.c	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
helpers.h	target-arm: Move Neon VZIP to helper functions	2011-02-20 17:31:53 +01:00
iwmmxt_helper.c	Update to a hopefully more future proof FSF address	2009-07-16 20:47:01 +00:00
machine.c	target-arm: Implement cp15 VA->PA translation	2011-03-06 23:37:18 +01:00
neon_helper.c	target-arm: Fix unsigned VQRSHL by large shift counts	2011-02-20 17:43:01 +01:00
op_addsub.h	target-arm: fix addsub/subadd implementation	2010-07-01 23:45:29 +02:00
op_helper.c	Set the right overflow bit for neon 32 and 64 bit saturating add/sub.	2011-02-04 20:57:41 +01:00
translate.c	target-arm: Implement a minimal set of cp14 debug registers	2011-03-07 09:46:19 +01:00