397 lines
11 KiB
C
397 lines
11 KiB
C
/*
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* XEN platform pci device, formerly known as the event channel device
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*
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* Copyright (c) 2003-2004 Intel Corp.
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* Copyright (c) 2006 XenSource
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include <assert.h>
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#include "hw.h"
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#include "pc.h"
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#include "pci.h"
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#include "irq.h"
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#include "xen_common.h"
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#include "net.h"
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#include "xen_backend.h"
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#include "trace.h"
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#include "exec-memory.h"
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#include <xenguest.h>
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//#define DEBUG_PLATFORM
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#ifdef DEBUG_PLATFORM
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#define DPRINTF(fmt, ...) do { \
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fprintf(stderr, "xen_platform: " fmt, ## __VA_ARGS__); \
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} while (0)
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#else
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#define DPRINTF(fmt, ...) do { } while (0)
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#endif
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#define PFFLAG_ROM_LOCK 1 /* Sets whether ROM memory area is RW or RO */
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typedef struct PCIXenPlatformState {
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PCIDevice pci_dev;
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MemoryRegion fixed_io;
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MemoryRegion bar;
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MemoryRegion mmio_bar;
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uint8_t flags; /* used only for version_id == 2 */
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int drivers_blacklisted;
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uint16_t driver_product_version;
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/* Log from guest drivers */
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char log_buffer[4096];
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int log_buffer_off;
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} PCIXenPlatformState;
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#define XEN_PLATFORM_IOPORT 0x10
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/* Send bytes to syslog */
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static void log_writeb(PCIXenPlatformState *s, char val)
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{
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if (val == '\n' || s->log_buffer_off == sizeof(s->log_buffer) - 1) {
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/* Flush buffer */
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s->log_buffer[s->log_buffer_off] = 0;
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trace_xen_platform_log(s->log_buffer);
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s->log_buffer_off = 0;
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} else {
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s->log_buffer[s->log_buffer_off++] = val;
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}
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}
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/* Xen Platform, Fixed IOPort */
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#define UNPLUG_ALL_IDE_DISKS 1
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#define UNPLUG_ALL_NICS 2
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#define UNPLUG_AUX_IDE_DISKS 4
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static void unplug_nic(PCIBus *b, PCIDevice *d)
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{
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if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
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PCI_CLASS_NETWORK_ETHERNET) {
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qdev_unplug(&(d->qdev));
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}
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}
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static void pci_unplug_nics(PCIBus *bus)
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{
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pci_for_each_device(bus, 0, unplug_nic);
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}
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static void unplug_disks(PCIBus *b, PCIDevice *d)
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{
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if (pci_get_word(d->config + PCI_CLASS_DEVICE) ==
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PCI_CLASS_STORAGE_IDE) {
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qdev_unplug(&(d->qdev));
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}
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}
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static void pci_unplug_disks(PCIBus *bus)
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{
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pci_for_each_device(bus, 0, unplug_disks);
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}
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static void platform_fixed_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0:
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/* Unplug devices. Value is a bitmask of which devices to
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unplug, with bit 0 the IDE devices, bit 1 the network
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devices, and bit 2 the non-primary-master IDE devices. */
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if (val & UNPLUG_ALL_IDE_DISKS) {
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DPRINTF("unplug disks\n");
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qemu_aio_flush();
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bdrv_flush_all();
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pci_unplug_disks(s->pci_dev.bus);
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}
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if (val & UNPLUG_ALL_NICS) {
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DPRINTF("unplug nics\n");
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pci_unplug_nics(s->pci_dev.bus);
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}
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if (val & UNPLUG_AUX_IDE_DISKS) {
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DPRINTF("unplug auxiliary disks not supported\n");
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}
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break;
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case 2:
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switch (val) {
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case 1:
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DPRINTF("Citrix Windows PV drivers loaded in guest\n");
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break;
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case 0:
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DPRINTF("Guest claimed to be running PV product 0?\n");
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break;
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default:
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DPRINTF("Unknown PV product %d loaded in guest\n", val);
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break;
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}
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s->driver_product_version = val;
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break;
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}
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}
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static void platform_fixed_ioport_writel(void *opaque, uint32_t addr,
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uint32_t val)
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{
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switch (addr) {
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case 0:
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/* PV driver version */
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break;
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}
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}
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static void platform_fixed_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0: /* Platform flags */ {
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hvmmem_type_t mem_type = (val & PFFLAG_ROM_LOCK) ?
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HVMMEM_ram_ro : HVMMEM_ram_rw;
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if (xc_hvm_set_mem_type(xen_xc, xen_domid, mem_type, 0xc0, 0x40)) {
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DPRINTF("unable to change ro/rw state of ROM memory area!\n");
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} else {
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s->flags = val & PFFLAG_ROM_LOCK;
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DPRINTF("changed ro/rw state of ROM memory area. now is %s state.\n",
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(mem_type == HVMMEM_ram_ro ? "ro":"rw"));
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}
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break;
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}
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case 2:
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log_writeb(s, val);
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break;
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}
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}
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static uint32_t platform_fixed_ioport_readw(void *opaque, uint32_t addr)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0:
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if (s->drivers_blacklisted) {
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/* The drivers will recognise this magic number and refuse
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* to do anything. */
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return 0xd249;
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} else {
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/* Magic value so that you can identify the interface. */
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return 0x49d2;
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}
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default:
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return 0xffff;
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}
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}
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static uint32_t platform_fixed_ioport_readb(void *opaque, uint32_t addr)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0:
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/* Platform flags */
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return s->flags;
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case 2:
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/* Version number */
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return 1;
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default:
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return 0xff;
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}
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}
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static void platform_fixed_ioport_reset(void *opaque)
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{
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PCIXenPlatformState *s = opaque;
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platform_fixed_ioport_writeb(s, 0, 0);
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}
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const MemoryRegionPortio xen_platform_ioport[] = {
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{ 0, 16, 4, .write = platform_fixed_ioport_writel, },
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{ 0, 16, 2, .write = platform_fixed_ioport_writew, },
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{ 0, 16, 1, .write = platform_fixed_ioport_writeb, },
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{ 0, 16, 2, .read = platform_fixed_ioport_readw, },
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{ 0, 16, 1, .read = platform_fixed_ioport_readb, },
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PORTIO_END_OF_LIST()
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};
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static const MemoryRegionOps platform_fixed_io_ops = {
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.old_portio = xen_platform_ioport,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void platform_fixed_ioport_init(PCIXenPlatformState* s)
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{
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memory_region_init_io(&s->fixed_io, &platform_fixed_io_ops, s,
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"xen-fixed", 16);
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memory_region_add_subregion(get_system_io(), XEN_PLATFORM_IOPORT,
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&s->fixed_io);
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}
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/* Xen Platform PCI Device */
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static uint32_t xen_platform_ioport_readb(void *opaque, uint32_t addr)
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{
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if (addr == 0) {
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return platform_fixed_ioport_readb(opaque, 0);
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} else {
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return ~0u;
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}
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}
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static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
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{
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PCIXenPlatformState *s = opaque;
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switch (addr) {
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case 0: /* Platform flags */
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platform_fixed_ioport_writeb(opaque, 0, val);
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break;
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case 8:
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log_writeb(s, val);
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break;
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default:
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break;
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}
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}
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static MemoryRegionPortio xen_pci_portio[] = {
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{ 0, 0x100, 1, .read = xen_platform_ioport_readb, },
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{ 0, 0x100, 1, .write = xen_platform_ioport_writeb, },
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PORTIO_END_OF_LIST()
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};
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static const MemoryRegionOps xen_pci_io_ops = {
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.old_portio = xen_pci_portio,
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};
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static void platform_ioport_bar_setup(PCIXenPlatformState *d)
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{
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memory_region_init_io(&d->bar, &xen_pci_io_ops, d, "xen-pci", 0x100);
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}
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static uint64_t platform_mmio_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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DPRINTF("Warning: attempted read from physical address "
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"0x" TARGET_FMT_plx " in xen platform mmio space\n", addr);
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return 0;
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}
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static void platform_mmio_write(void *opaque, target_phys_addr_t addr,
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uint64_t val, unsigned size)
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{
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DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical "
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"address 0x" TARGET_FMT_plx " in xen platform mmio space\n",
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val, addr);
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}
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static const MemoryRegionOps platform_mmio_handler = {
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.read = &platform_mmio_read,
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.write = &platform_mmio_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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static void platform_mmio_setup(PCIXenPlatformState *d)
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{
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memory_region_init_io(&d->mmio_bar, &platform_mmio_handler, d,
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"xen-mmio", 0x1000000);
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}
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static int xen_platform_post_load(void *opaque, int version_id)
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{
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PCIXenPlatformState *s = opaque;
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platform_fixed_ioport_writeb(s, 0, s->flags);
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return 0;
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}
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static const VMStateDescription vmstate_xen_platform = {
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.name = "platform",
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.version_id = 4,
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.minimum_version_id = 4,
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.minimum_version_id_old = 4,
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.post_load = xen_platform_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(pci_dev, PCIXenPlatformState),
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VMSTATE_UINT8(flags, PCIXenPlatformState),
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VMSTATE_END_OF_LIST()
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}
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};
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static int xen_platform_initfn(PCIDevice *dev)
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{
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PCIXenPlatformState *d = DO_UPCAST(PCIXenPlatformState, pci_dev, dev);
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uint8_t *pci_conf;
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pci_conf = d->pci_dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
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pci_config_set_prog_interface(pci_conf, 0);
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pci_conf[PCI_INTERRUPT_PIN] = 1;
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platform_ioport_bar_setup(d);
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pci_register_bar(&d->pci_dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->bar);
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/* reserve 16MB mmio address for share memory*/
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platform_mmio_setup(d);
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pci_register_bar(&d->pci_dev, 1, PCI_BASE_ADDRESS_MEM_PREFETCH,
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&d->mmio_bar);
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platform_fixed_ioport_init(d);
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return 0;
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}
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static void platform_reset(DeviceState *dev)
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{
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PCIXenPlatformState *s = DO_UPCAST(PCIXenPlatformState, pci_dev.qdev, dev);
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platform_fixed_ioport_reset(s);
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}
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static PCIDeviceInfo xen_platform_info = {
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.init = xen_platform_initfn,
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.qdev.name = "xen-platform",
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.qdev.desc = "XEN platform pci device",
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.qdev.size = sizeof(PCIXenPlatformState),
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.qdev.vmsd = &vmstate_xen_platform,
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.qdev.reset = platform_reset,
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.vendor_id = PCI_VENDOR_ID_XEN,
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.device_id = PCI_DEVICE_ID_XEN_PLATFORM,
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.class_id = PCI_CLASS_OTHERS << 8 | 0x80,
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.subsystem_vendor_id = PCI_VENDOR_ID_XEN,
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.subsystem_id = PCI_DEVICE_ID_XEN_PLATFORM,
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.revision = 1,
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};
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static void xen_platform_register(void)
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{
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pci_qdev_register(&xen_platform_info);
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}
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device_init(xen_platform_register);
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