416 lines
12 KiB
C
416 lines
12 KiB
C
#if !defined (__MIPS_CPU_H__)
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#define __MIPS_CPU_H__
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#include "mips-defs.h"
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#include "cpu-defs.h"
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#include "config.h"
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#include "softfloat.h"
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typedef union fpr_t fpr_t;
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union fpr_t {
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double d;
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float f;
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uint32_t u[2];
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};
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#if defined(MIPS_USES_R4K_TLB)
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typedef struct tlb_t tlb_t;
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struct tlb_t {
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target_ulong VPN;
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target_ulong end;
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uint8_t ASID;
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uint8_t G;
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uint8_t C[2];
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uint8_t V[2];
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uint8_t D[2];
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target_ulong PFN[2];
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};
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#endif
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typedef struct CPUMIPSState CPUMIPSState;
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struct CPUMIPSState {
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/* General integer registers */
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target_ulong gpr[32];
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/* Special registers */
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target_ulong PC;
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uint32_t HI, LO;
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uint32_t DCR; /* ? */
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#if defined(MIPS_USES_FPU)
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/* Floating point registers */
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fpr_t fpr[16];
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/* Floating point special purpose registers */
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uint32_t fcr0;
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uint32_t fcr25;
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uint32_t fcr26;
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uint32_t fcr28;
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uint32_t fcsr;
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#endif
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#if defined(MIPS_USES_R4K_TLB)
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tlb_t tlb[16];
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#endif
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uint32_t CP0_index;
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uint32_t CP0_random;
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uint32_t CP0_EntryLo0;
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uint32_t CP0_EntryLo1;
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uint32_t CP0_Context;
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uint32_t CP0_PageMask;
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uint32_t CP0_Wired;
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uint32_t CP0_BadVAddr;
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uint32_t CP0_Count;
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uint32_t CP0_EntryHi;
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uint32_t CP0_Compare;
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uint32_t CP0_Status;
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#define CP0St_CU3 31
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#define CP0St_CU2 30
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#define CP0St_CU1 29
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#define CP0St_CU0 28
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#define CP0St_RP 27
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#define CP0St_RE 25
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#define CP0St_BEV 22
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#define CP0St_TS 21
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#define CP0St_SR 20
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#define CP0St_NMI 19
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#define CP0St_IM 8
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#define CP0St_UM 4
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#define CP0St_ERL 2
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#define CP0St_EXL 1
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#define CP0St_IE 0
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uint32_t CP0_Cause;
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#define CP0Ca_IV 23
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uint32_t CP0_EPC;
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uint32_t CP0_PRid;
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uint32_t CP0_Config0;
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#define CP0C0_M 31
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#define CP0C0_K23 28
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#define CP0C0_KU 25
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#define CP0C0_MDU 20
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#define CP0C0_MM 17
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#define CP0C0_BM 16
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#define CP0C0_BE 15
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#define CP0C0_AT 13
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#define CP0C0_AR 10
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#define CP0C0_MT 7
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#define CP0C0_K0 0
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uint32_t CP0_Config1;
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#define CP0C1_MMU 25
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#define CP0C1_IS 22
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#define CP0C1_IL 19
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#define CP0C1_IA 16
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#define CP0C1_DS 13
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#define CP0C1_DL 10
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#define CP0C1_DA 7
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#define CP0C1_PC 4
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#define CP0C1_WR 3
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#define CP0C1_CA 2
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#define CP0C1_EP 1
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#define CP0C1_FP 0
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uint32_t CP0_LLAddr;
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uint32_t CP0_WatchLo;
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uint32_t CP0_WatchHi;
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uint32_t CP0_Debug;
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#define CPDB_DBD 31
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#define CP0DB_DM 30
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#define CP0DB_LSNM 28
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#define CP0DB_Doze 27
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#define CP0DB_Halt 26
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#define CP0DB_CNT 25
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#define CP0DB_IBEP 24
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#define CP0DB_DBEP 21
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#define CP0DB_IEXI 20
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#define CP0DB_VER 15
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#define CP0DB_DEC 10
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#define CP0DB_SSt 8
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#define CP0DB_DINT 5
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#define CP0DB_DIB 4
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#define CP0DB_DDBS 3
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#define CP0DB_DDBL 2
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#define CP0DB_DBp 1
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#define CP0DB_DSS 0
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uint32_t CP0_DEPC;
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uint32_t CP0_TagLo;
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uint32_t CP0_DataLo;
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uint32_t CP0_ErrorEPC;
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uint32_t CP0_DESAVE;
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/* Qemu */
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#if defined (USE_HOST_FLOAT_REGS) && defined(MIPS_USES_FPU)
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double ft0, ft1, ft2;
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#endif
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struct QEMUTimer *timer; /* Internal timer */
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int interrupt_request;
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jmp_buf jmp_env;
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int exception_index;
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int error_code;
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int user_mode_only; /* user mode only simulation */
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uint32_t hflags; /* CPU State */
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/* TMASK defines different execution modes */
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#define MIPS_HFLAGS_TMASK 0x00FF
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#define MIPS_HFLAG_MODE 0x001F /* execution modes */
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#define MIPS_HFLAG_UM 0x0001 /* user mode */
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#define MIPS_HFLAG_ERL 0x0002 /* Error mode */
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#define MIPS_HFLAG_EXL 0x0004 /* Exception mode */
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#define MIPS_HFLAG_DM 0x0008 /* Debug mode */
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#define MIPS_HFLAG_SM 0x0010 /* Supervisor mode */
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#define MIPS_HFLAG_RE 0x0040 /* Reversed endianness */
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#define MIPS_HFLAG_DS 0x0080 /* In / out of delay slot */
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/* Those flags keep the branch state if the translation is interrupted
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* between the branch instruction and the delay slot
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*/
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#define MIPS_HFLAG_BMASK 0x0F00
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#define MIPS_HFLAG_B 0x0100 /* Unconditional branch */
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#define MIPS_HFLAG_BC 0x0200 /* Conditional branch */
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#define MIPS_HFLAG_BL 0x0400 /* Likely branch */
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#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
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target_ulong btarget; /* Jump / branch target */
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int bcond; /* Branch condition (if needed) */
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struct TranslationBlock *current_tb; /* currently executing TB */
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/* soft mmu support */
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/* in order to avoid passing too many arguments to the memory
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write helpers, we store some rarely used information in the CPU
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context) */
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target_ulong mem_write_pc; /* host pc at which the memory was
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written */
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unsigned long mem_write_vaddr; /* target virtual addr at which the
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memory was written */
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/* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
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CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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/* ice debug support */
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target_ulong breakpoints[MAX_BREAKPOINTS];
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int nb_breakpoints;
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int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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/* user data */
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void *opaque;
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};
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#include "cpu-all.h"
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/* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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/* 1 bit to define user level / supervisor access */
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ACCESS_USER = 0x00,
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ACCESS_SUPER = 0x01,
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/* 1 bit to indicate direction */
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ACCESS_STORE = 0x02,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */
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ACCESS_INT = 0x20, /* Integer load/store access */
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ACCESS_FLOAT = 0x30, /* floating point load/store access */
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};
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/* Exceptions */
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enum {
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EXCP_NONE = -1,
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EXCP_RESET = 0,
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EXCP_SRESET,
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EXCP_DSS,
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EXCP_DINT,
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EXCP_NMI,
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EXCP_MCHECK,
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EXCP_EXT_INTERRUPT,
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EXCP_DFWATCH,
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EXCP_DIB, /* 8 */
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EXCP_IWATCH,
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EXCP_AdEL,
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EXCP_AdES,
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EXCP_TLBF,
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EXCP_IBE,
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EXCP_DBp,
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EXCP_SYSCALL,
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EXCP_BREAK,
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EXCP_CpU, /* 16 */
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EXCP_RI,
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EXCP_OVERFLOW,
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EXCP_TRAP,
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EXCP_DDBS,
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EXCP_DWATCH,
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EXCP_LAE, /* 22 */
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EXCP_SAE,
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EXCP_LTLBL,
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EXCP_TLBL,
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EXCP_TLBS,
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EXCP_DBE,
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EXCP_DDBL,
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EXCP_MTCP0 = 0x104, /* mtmsr instruction: */
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/* may change privilege level */
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EXCP_BRANCH = 0x108, /* branch instruction */
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EXCP_ERET = 0x10C, /* return from interrupt */
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EXCP_SYSCALL_USER = 0x110, /* System call in user mode only */
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EXCP_FLUSH = 0x109,
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};
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/* MIPS opcodes */
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#define EXT_SPECIAL 0x100
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#define EXT_SPECIAL2 0x200
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#define EXT_REGIMM 0x300
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#define EXT_CP0 0x400
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#define EXT_CP1 0x500
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#define EXT_CP2 0x600
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#define EXT_CP3 0x700
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enum {
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/* indirect opcode tables */
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OPC_SPECIAL = 0x00,
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OPC_BREGIMM = 0x01,
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OPC_CP0 = 0x10,
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OPC_CP1 = 0x11,
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OPC_CP2 = 0x12,
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OPC_CP3 = 0x13,
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OPC_SPECIAL2 = 0x1C,
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/* arithmetic with immediate */
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OPC_ADDI = 0x08,
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OPC_ADDIU = 0x09,
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OPC_SLTI = 0x0A,
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OPC_SLTIU = 0x0B,
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OPC_ANDI = 0x0C,
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OPC_ORI = 0x0D,
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OPC_XORI = 0x0E,
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OPC_LUI = 0x0F,
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/* Jump and branches */
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OPC_J = 0x02,
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OPC_JAL = 0x03,
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OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
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OPC_BEQL = 0x14,
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OPC_BNE = 0x05,
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OPC_BNEL = 0x15,
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OPC_BLEZ = 0x06,
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OPC_BLEZL = 0x16,
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OPC_BGTZ = 0x07,
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OPC_BGTZL = 0x17,
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OPC_JALX = 0x1D, /* MIPS 16 only */
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/* Load and stores */
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OPC_LB = 0x20,
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OPC_LH = 0x21,
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OPC_LWL = 0x22,
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OPC_LW = 0x23,
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OPC_LBU = 0x24,
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OPC_LHU = 0x25,
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OPC_LWR = 0x26,
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OPC_SB = 0x28,
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OPC_SH = 0x29,
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OPC_SWL = 0x2A,
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OPC_SW = 0x2B,
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OPC_SWR = 0x2E,
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OPC_LL = 0x30,
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OPC_SC = 0x38,
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/* Floating point load/store */
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OPC_LWC1 = 0x31,
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OPC_LWC2 = 0x32,
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OPC_LDC1 = 0x35,
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OPC_LDC2 = 0x36,
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OPC_SWC1 = 0x39,
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OPC_SWC2 = 0x3A,
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OPC_SDC1 = 0x3D,
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OPC_SDC2 = 0x3E,
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/* Cache and prefetch */
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OPC_CACHE = 0x2F,
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OPC_PREF = 0x33,
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};
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/* MIPS special opcodes */
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enum {
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/* Shifts */
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OPC_SLL = 0x00 | EXT_SPECIAL,
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/* NOP is SLL r0, r0, 0 */
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/* SSNOP is SLL r0, r0, 1 */
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OPC_SRL = 0x02 | EXT_SPECIAL,
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OPC_SRA = 0x03 | EXT_SPECIAL,
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OPC_SLLV = 0x04 | EXT_SPECIAL,
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OPC_SRLV = 0x06 | EXT_SPECIAL,
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OPC_SRAV = 0x07 | EXT_SPECIAL,
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/* Multiplication / division */
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OPC_MULT = 0x18 | EXT_SPECIAL,
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OPC_MULTU = 0x19 | EXT_SPECIAL,
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OPC_DIV = 0x1A | EXT_SPECIAL,
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OPC_DIVU = 0x1B | EXT_SPECIAL,
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/* 2 registers arithmetic / logic */
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OPC_ADD = 0x20 | EXT_SPECIAL,
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OPC_ADDU = 0x21 | EXT_SPECIAL,
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OPC_SUB = 0x22 | EXT_SPECIAL,
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OPC_SUBU = 0x23 | EXT_SPECIAL,
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OPC_AND = 0x24 | EXT_SPECIAL,
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OPC_OR = 0x25 | EXT_SPECIAL,
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OPC_XOR = 0x26 | EXT_SPECIAL,
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OPC_NOR = 0x27 | EXT_SPECIAL,
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OPC_SLT = 0x2A | EXT_SPECIAL,
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OPC_SLTU = 0x2B | EXT_SPECIAL,
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/* Jumps */
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OPC_JR = 0x08 | EXT_SPECIAL,
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OPC_JALR = 0x09 | EXT_SPECIAL,
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/* Traps */
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OPC_TGE = 0x30 | EXT_SPECIAL,
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OPC_TGEU = 0x31 | EXT_SPECIAL,
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OPC_TLT = 0x32 | EXT_SPECIAL,
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OPC_TLTU = 0x33 | EXT_SPECIAL,
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OPC_TEQ = 0x34 | EXT_SPECIAL,
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OPC_TNE = 0x36 | EXT_SPECIAL,
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/* HI / LO registers load & stores */
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OPC_MFHI = 0x10 | EXT_SPECIAL,
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OPC_MTHI = 0x11 | EXT_SPECIAL,
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OPC_MFLO = 0x12 | EXT_SPECIAL,
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OPC_MTLO = 0x13 | EXT_SPECIAL,
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/* Conditional moves */
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OPC_MOVZ = 0x0A | EXT_SPECIAL,
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OPC_MOVN = 0x0B | EXT_SPECIAL,
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OPC_MOVCI = 0x01 | EXT_SPECIAL,
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/* Special */
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OPC_PMON = 0x05 | EXT_SPECIAL,
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OPC_SYSCALL = 0x0C | EXT_SPECIAL,
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OPC_BREAK = 0x0D | EXT_SPECIAL,
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OPC_SYNC = 0x0F | EXT_SPECIAL,
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};
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enum {
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/* Mutiply & xxx operations */
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OPC_MADD = 0x00 | EXT_SPECIAL2,
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OPC_MADDU = 0x01 | EXT_SPECIAL2,
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OPC_MUL = 0x02 | EXT_SPECIAL2,
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OPC_MSUB = 0x04 | EXT_SPECIAL2,
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OPC_MSUBU = 0x05 | EXT_SPECIAL2,
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/* Misc */
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OPC_CLZ = 0x20 | EXT_SPECIAL2,
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OPC_CLO = 0x21 | EXT_SPECIAL2,
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/* Special */
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OPC_SDBBP = 0x3F | EXT_SPECIAL2,
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};
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/* Branch REGIMM */
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enum {
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OPC_BLTZ = 0x00 | EXT_REGIMM,
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OPC_BLTZL = 0x02 | EXT_REGIMM,
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OPC_BGEZ = 0x01 | EXT_REGIMM,
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OPC_BGEZL = 0x03 | EXT_REGIMM,
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OPC_BLTZAL = 0x10 | EXT_REGIMM,
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OPC_BLTZALL = 0x12 | EXT_REGIMM,
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OPC_BGEZAL = 0x11 | EXT_REGIMM,
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OPC_BGEZALL = 0x13 | EXT_REGIMM,
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OPC_TGEI = 0x08 | EXT_REGIMM,
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OPC_TGEIU = 0x09 | EXT_REGIMM,
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OPC_TLTI = 0x0A | EXT_REGIMM,
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OPC_TLTIU = 0x0B | EXT_REGIMM,
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OPC_TEQI = 0x0C | EXT_REGIMM,
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OPC_TNEI = 0x0E | EXT_REGIMM,
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};
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enum {
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/* Coprocessor 0 (MMU) */
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OPC_MFC0 = 0x00 | EXT_CP0,
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OPC_MTC0 = 0x04 | EXT_CP0,
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OPC_TLBR = 0x01 | EXT_CP0,
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OPC_TLBWI = 0x02 | EXT_CP0,
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OPC_TLBWR = 0x06 | EXT_CP0,
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OPC_TLBP = 0x08 | EXT_CP0,
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OPC_ERET = 0x18 | EXT_CP0,
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OPC_DERET = 0x1F | EXT_CP0,
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OPC_WAIT = 0x20 | EXT_CP0,
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};
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int cpu_mips_exec(CPUMIPSState *s);
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CPUMIPSState *cpu_mips_init(void);
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uint32_t cpu_mips_get_clock (void);
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#endif /* !defined (__MIPS_CPU_H__) */
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