diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 834c08ddd..c7291ed90 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -33,17 +33,7 @@ typedef uint64_t ppc_gpr_t;
 
 #else /* defined (TARGET_PPC64) */
 /* PowerPC 32 definitions */
-#if (HOST_LONG_BITS >= 64)
-/* When using 64 bits temporary registers,
- * we can use 64 bits GPR with no extra cost
- * It's even an optimization as this will prevent
- * the compiler to do unuseful masking in the micro-ops.
- */
-typedef uint64_t ppc_gpr_t;
-#else /* (HOST_LONG_BITS >= 64) */
 typedef uint32_t ppc_gpr_t;
-#endif /* (HOST_LONG_BITS >= 64) */
-
 #define TARGET_LONG_BITS 32
 
 #if defined(TARGET_PPCEMB)
@@ -541,7 +531,7 @@ struct CPUPPCState {
     /* First are the most commonly used resources
      * during translated code execution
      */
-#if (HOST_LONG_BITS == 32)
+#if (TARGET_LONG_BITS > HOST_LONG_BITS) || !defined(TARGET_PPC64)
     /* temporary fixed-point registers
      * used to emulate 64 bits registers on 32 bits hosts
      */
diff --git a/target-ppc/op_template.h b/target-ppc/op_template.h
index e6d6afac5..8c65e4918 100644
--- a/target-ppc/op_template.h
+++ b/target-ppc/op_template.h
@@ -18,91 +18,6 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  */
 
-/* General purpose registers moves */
-void OPPROTO glue(op_load_gpr_T0_gpr, REG) (void)
-{
-    T0 = env->gpr[REG];
-    RETURN();
-}
-
-void OPPROTO glue(op_load_gpr_T1_gpr, REG) (void)
-{
-    T1 = env->gpr[REG];
-    RETURN();
-}
-
-void OPPROTO glue(op_load_gpr_T2_gpr, REG) (void)
-{
-    T2 = env->gpr[REG];
-    RETURN();
-}
-
-void OPPROTO glue(op_store_T0_gpr_gpr, REG) (void)
-{
-    env->gpr[REG] = T0;
-    RETURN();
-}
-
-void OPPROTO glue(op_store_T1_gpr_gpr, REG) (void)
-{
-    env->gpr[REG] = T1;
-    RETURN();
-}
-
-#if 0 // unused
-void OPPROTO glue(op_store_T2_gpr_gpr, REG) (void)
-{
-    env->gpr[REG] = T2;
-    RETURN();
-}
-#endif
-
-/* General purpose registers containing vector operands moves */
-#if !defined(TARGET_PPC64)
-void OPPROTO glue(op_load_gpr64_T0_gpr, REG) (void)
-{
-    T0_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
-    RETURN();
-}
-
-void OPPROTO glue(op_load_gpr64_T1_gpr, REG) (void)
-{
-    T1_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
-    RETURN();
-}
-
-#if 0 // unused
-void OPPROTO glue(op_load_gpr64_T2_gpr, REG) (void)
-{
-    T2_64 = (uint64_t)env->gpr[REG] | ((uint64_t)env->gprh[REG] << 32);
-    RETURN();
-}
-#endif
-
-void OPPROTO glue(op_store_T0_gpr64_gpr, REG) (void)
-{
-    env->gpr[REG] = T0_64;
-    env->gprh[REG] = T0_64 >> 32;
-    RETURN();
-}
-
-void OPPROTO glue(op_store_T1_gpr64_gpr, REG) (void)
-{
-    env->gpr[REG] = T1_64;
-    env->gprh[REG] = T1_64 >> 32;
-    RETURN();
-}
-
-#if 0 // unused
-void OPPROTO glue(op_store_T2_gpr64_gpr, REG) (void)
-{
-    env->gpr[REG] = T2_64;
-    env->gprh[REG] = T2_64 >> 32;
-    RETURN();
-}
-#endif
-#endif /* !defined(TARGET_PPC64) */
-
 /* Altivec registers moves */
 void OPPROTO glue(op_load_avr_A0_avr, REG) (void)
 {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 906893657..beb45c257 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -44,15 +44,37 @@
 /*****************************************************************************/
 /* Code translation helpers                                                  */
 
-static TCGv cpu_env, cpu_T[3];
+/* global register indexes */
+static TCGv cpu_env;
+static char cpu_reg_names[10*3 + 22*4
+#if !defined(TARGET_PPC64)
+    + 10*4 + 22*5
+#endif
+];
+static TCGv cpu_gpr[32];
+#if !defined(TARGET_PPC64)
+static TCGv cpu_gprh[32];
+#endif
+
+/* dyngen register indexes */
+static TCGv cpu_T[3];
+#if defined(TARGET_PPC64)
+#define cpu_T64 cpu_T
+#else
+static TCGv cpu_T64[3];
+#endif
 
 #include "gen-icount.h"
 
 void ppc_translate_init(void)
 {
+    int i;
+    char* p;
     static int done_init = 0;
+
     if (done_init)
         return;
+
     cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
 #if TARGET_LONG_BITS > HOST_LONG_BITS
     cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
@@ -66,6 +88,31 @@ void ppc_translate_init(void)
     cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
     cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
 #endif
+#if !defined(TARGET_PPC64)
+    cpu_T64[0] = tcg_global_mem_new(TCG_TYPE_I64,
+                                    TCG_AREG0, offsetof(CPUState, t0),
+                                    "T0_64");
+    cpu_T64[1] = tcg_global_mem_new(TCG_TYPE_I64,
+                                    TCG_AREG0, offsetof(CPUState, t1),
+                                    "T1_64");
+    cpu_T64[2] = tcg_global_mem_new(TCG_TYPE_I64,
+                                    TCG_AREG0, offsetof(CPUState, t2),
+                                    "T2_64");
+#endif
+    
+    p = cpu_reg_names;
+    for (i = 0; i < 32; i++) {
+        sprintf(p, "r%d", i);
+        cpu_gpr[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
+                                        offsetof(CPUState, gpr[i]), p);
+        p += (i < 10) ? 3 : 4;
+#if !defined(TARGET_PPC64)
+        sprintf(p, "r%dH", i);
+        cpu_gprh[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+                                         offsetof(CPUState, gprh[i]), p);
+        p += (i < 10) ? 4 : 5;
+#endif
+    }
 
     /* register helpers */
 #undef DEF_HELPER
@@ -126,17 +173,6 @@ GEN8(gen_op_store_T0_crf, gen_op_store_T0_crf_crf);
 GEN8(gen_op_store_T1_crf, gen_op_store_T1_crf_crf);
 #endif
 
-/* General purpose registers moves */
-GEN32(gen_op_load_gpr_T0, gen_op_load_gpr_T0_gpr);
-GEN32(gen_op_load_gpr_T1, gen_op_load_gpr_T1_gpr);
-GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr);
-
-GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr);
-GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr);
-#if 0 // unused
-GEN32(gen_op_store_T2_gpr, gen_op_store_T2_gpr_gpr);
-#endif
-
 /* floating point registers moves */
 GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fpr);
 GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fpr);
@@ -667,10 +703,10 @@ static opc_handler_t invalid_handler = {
 #define __GEN_INT_ARITH2(name, opc1, opc2, opc3, inval, type)                 \
 GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -678,10 +714,10 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 #define __GEN_INT_ARITH2_O(name, opc1, opc2, opc3, inval, type)               \
 GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -689,18 +725,18 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 #define __GEN_INT_ARITH1(name, opc1, opc2, opc3, type)                        \
 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
 #define __GEN_INT_ARITH1_O(name, opc1, opc2, opc3, type)                      \
 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -723,13 +759,13 @@ __GEN_INT_ARITH1_O(name##o, opc1, opc2, opc3 | 0x10, type)
 #define __GEN_INT_ARITH2_64(name, opc1, opc2, opc3, inval, type)              \
 GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     if (ctx->sf_mode)                                                         \
         gen_op_##name##_64();                                                 \
     else                                                                      \
         gen_op_##name();                                                      \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -737,13 +773,13 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 #define __GEN_INT_ARITH2_O_64(name, opc1, opc2, opc3, inval, type)            \
 GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     if (ctx->sf_mode)                                                         \
         gen_op_##name##_64();                                                 \
     else                                                                      \
         gen_op_##name();                                                      \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -751,24 +787,24 @@ GEN_HANDLER(name, opc1, opc2, opc3, inval, type)                              \
 #define __GEN_INT_ARITH1_64(name, opc1, opc2, opc3, type)                     \
 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
     if (ctx->sf_mode)                                                         \
         gen_op_##name##_64();                                                 \
     else                                                                      \
         gen_op_##name();                                                      \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
 #define __GEN_INT_ARITH1_O_64(name, opc1, opc2, opc3, type)                   \
 GEN_HANDLER(name, opc1, opc2, opc3, 0x0000F800, type)                         \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
     if (ctx->sf_mode)                                                         \
         gen_op_##name##_64();                                                 \
     else                                                                      \
         gen_op_##name();                                                      \
-    gen_op_store_T0_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -986,18 +1022,18 @@ GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* li case */
         tcg_gen_movi_tl(cpu_T[0], simm);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         if (likely(simm != 0))
             gen_op_addi(simm);
     }
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 /* addic */
 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
     target_long simm = SIMM(ctx->opcode);
 
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     if (likely(simm != 0)) {
         tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
         gen_op_addi(simm);
@@ -1010,14 +1046,14 @@ GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
     } else {
         gen_op_clear_xer_ca();
     }
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 /* addic. */
 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
     target_long simm = SIMM(ctx->opcode);
 
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     if (likely(simm != 0)) {
         tcg_gen_mov_tl(cpu_T[2], cpu_T[0]);
         gen_op_addi(simm);
@@ -1030,7 +1066,7 @@ GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
     } else {
         gen_op_clear_xer_ca();
     }
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     gen_set_Rc0(ctx);
 }
 /* addis */
@@ -1042,30 +1078,30 @@ GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* lis case */
         tcg_gen_movi_tl(cpu_T[0], simm << 16);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         if (likely(simm != 0))
             gen_op_addi(simm << 16);
     }
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 /* mulli */
 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_mulli(SIMM(ctx->opcode));
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 /* subfic */
 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode)
         gen_op_subfic_64(SIMM(ctx->opcode));
     else
 #endif
         gen_op_subfic(SIMM(ctx->opcode));
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 #if defined(TARGET_PPC64)
@@ -1086,8 +1122,8 @@ GEN_INT_ARITH2 (divdu,  0x1F, 0x09, 0x0E, PPC_64B);
 #define GEN_CMP(name, opc, type)                                              \
 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     if (ctx->sf_mode && (ctx->opcode & 0x00200000))                           \
         gen_op_##name##_64();                                                 \
     else                                                                      \
@@ -1098,8 +1134,8 @@ GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
 #define GEN_CMP(name, opc, type)                                              \
 GEN_HANDLER(name, 0x1F, 0x00, opc, 0x00400000, type)                          \
 {                                                                             \
-    gen_op_load_gpr_T0(rA(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
     gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
 }
@@ -1110,7 +1146,7 @@ GEN_CMP(cmp, 0x00, PPC_INTEGER);
 /* cmpi */
 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode && (ctx->opcode & 0x00200000))
         gen_op_cmpi_64(SIMM(ctx->opcode));
@@ -1124,7 +1160,7 @@ GEN_CMP(cmpl, 0x01, PPC_INTEGER);
 /* cmpli */
 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode && (ctx->opcode & 0x00200000))
         gen_op_cmpli_64(UIMM(ctx->opcode));
@@ -1143,24 +1179,24 @@ GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL)
     if (rA(ctx->opcode) == 0) {
         tcg_gen_movi_tl(cpu_T[0], 0);
     } else {
-        gen_op_load_gpr_T1(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
     }
-    gen_op_load_gpr_T2(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
     mask = 1 << (3 - (bi & 0x03));
     gen_op_load_crf_T0(bi >> 2);
     gen_op_test_true(mask);
     gen_op_isel();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 /***                            Integer logical                            ***/
 #define __GEN_LOGICAL2(name, opc2, opc3, type)                                \
 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000000, type)                         \
 {                                                                             \
-    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
-    gen_op_load_gpr_T1(rB(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);                       \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -1170,9 +1206,9 @@ __GEN_LOGICAL2(name, 0x1C, opc, type)
 #define GEN_LOGICAL1(name, opc, type)                                         \
 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)                          \
 {                                                                             \
-    gen_op_load_gpr_T0(rS(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);                       \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
     if (unlikely(Rc(ctx->opcode) != 0))                                       \
         gen_set_Rc0(ctx);                                                     \
 }
@@ -1184,17 +1220,17 @@ GEN_LOGICAL2(andc, 0x01, PPC_INTEGER);
 /* andi. */
 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     gen_op_andi_T0(UIMM(ctx->opcode));
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     gen_set_Rc0(ctx);
 }
 /* andis. */
 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     gen_op_andi_T0(UIMM(ctx->opcode) << 16);
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     gen_set_Rc0(ctx);
 }
 
@@ -1221,16 +1257,16 @@ GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER)
     rb = rB(ctx->opcode);
     /* Optimisation for mr. ri case */
     if (rs != ra || rs != rb) {
-        gen_op_load_gpr_T0(rs);
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
         if (rs != rb) {
-            gen_op_load_gpr_T1(rb);
+            tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
             gen_op_or();
         }
-        gen_op_store_T0_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
         if (unlikely(Rc(ctx->opcode) != 0))
             gen_set_Rc0(ctx);
     } else if (unlikely(Rc(ctx->opcode) != 0)) {
-        gen_op_load_gpr_T0(rs);
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rs]);
         gen_set_Rc0(ctx);
 #if defined(TARGET_PPC64)
     } else {
@@ -1286,15 +1322,15 @@ GEN_LOGICAL2(orc, 0x0C, PPC_INTEGER);
 /* xor & xor. */
 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     /* Optimisation for "set to zero" case */
     if (rS(ctx->opcode) != rB(ctx->opcode)) {
-        gen_op_load_gpr_T1(rB(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
         gen_op_xor();
     } else {
         tcg_gen_movi_tl(cpu_T[0], 0);
     }
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1308,10 +1344,10 @@ GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* XXX: should handle special NOPs for POWER series */
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(uimm != 0))
         gen_op_ori(uimm);
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 /* oris */
 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
@@ -1322,10 +1358,10 @@ GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* NOP */
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(uimm != 0))
         gen_op_ori(uimm << 16);
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 /* xori */
 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
@@ -1336,10 +1372,10 @@ GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* NOP */
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(uimm != 0))
         gen_op_xori(uimm);
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 
 /* xoris */
@@ -1351,23 +1387,23 @@ GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
         /* NOP */
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(uimm != 0))
         gen_op_xori(uimm << 16);
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 
 /* popcntb : PowerPC 2.03 specification */
 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode)
         gen_op_popcntb_64();
     else
 #endif
         gen_op_popcntb();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 
 #if defined(TARGET_PPC64)
@@ -1389,18 +1425,18 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
     sh = SH(ctx->opcode);
     if (likely(sh == 0)) {
         if (likely(mb == 0 && me == 31)) {
-            gen_op_load_gpr_T0(rS(ctx->opcode));
+            tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
             goto do_store;
         } else if (likely(mb == 31 && me == 0)) {
-            gen_op_load_gpr_T0(rA(ctx->opcode));
+            tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
             goto do_store;
         }
-        gen_op_load_gpr_T0(rS(ctx->opcode));
-        gen_op_load_gpr_T1(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
         goto do_mask;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
     gen_op_rotli32_T0(SH(ctx->opcode));
  do_mask:
 #if defined(TARGET_PPC64)
@@ -1412,7 +1448,7 @@ GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
     gen_op_andi_T1(~mask);
     gen_op_or();
  do_store:
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1424,7 +1460,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
     sh = SH(ctx->opcode);
     mb = MB(ctx->opcode);
     me = ME(ctx->opcode);
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(sh == 0)) {
         goto do_mask;
     }
@@ -1450,7 +1486,7 @@ GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 #endif
     gen_op_andi_T0(MASK(mb, me));
  do_store:
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1461,8 +1497,8 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 
     mb = MB(ctx->opcode);
     me = ME(ctx->opcode);
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_rotl32_T0_T1();
     if (unlikely(mb != 0 || me != 31)) {
 #if defined(TARGET_PPC64)
@@ -1471,7 +1507,7 @@ GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
 #endif
         gen_op_andi_T0(MASK(mb, me));
     }
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1527,7 +1563,7 @@ static always_inline void gen_andi_T1_64 (DisasContext *ctx, uint64_t mask)
 static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
                                       uint32_t me, uint32_t sh)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (likely(sh == 0)) {
         goto do_mask;
     }
@@ -1549,7 +1585,7 @@ static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
  do_mask:
     gen_andi_T0_64(ctx, MASK(mb, me));
  do_store:
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1587,13 +1623,13 @@ GEN_PPC64_R4(rldic, 0x1E, 0x04);
 static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
                                      uint32_t me)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_rotl64_T0_T1();
     if (unlikely(mb != 0 || me != 63)) {
         gen_andi_T0_64(ctx, MASK(mb, me));
     }
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1627,15 +1663,15 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
     me = 63 - sh;
     if (likely(sh == 0)) {
         if (likely(mb == 0)) {
-            gen_op_load_gpr_T0(rS(ctx->opcode));
+            tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
             goto do_store;
         }
-        gen_op_load_gpr_T0(rS(ctx->opcode));
-        gen_op_load_gpr_T1(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
         goto do_mask;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
     gen_op_rotli64_T0(sh);
  do_mask:
     mask = MASK(mb, me);
@@ -1643,7 +1679,7 @@ static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
     gen_andi_T1_64(ctx, ~mask);
     gen_op_or();
  do_store:
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1659,7 +1695,7 @@ __GEN_LOGICAL2(sraw, 0x18, 0x18, PPC_INTEGER);
 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
 {
     int mb, me;
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (SH(ctx->opcode) != 0) {
         tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
         mb = 32 - SH(ctx->opcode);
@@ -1670,7 +1706,7 @@ GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER)
 #endif
         gen_op_srawi(SH(ctx->opcode), MASK(mb, me));
     }
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -1688,7 +1724,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
     uint64_t mask;
     int sh, mb, me;
 
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     sh = SH(ctx->opcode) + (n << 5);
     if (sh != 0) {
         tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
@@ -1697,7 +1733,7 @@ static always_inline void gen_sradi (DisasContext *ctx, int n)
         mask = MASK(mb, me);
         gen_op_sradi(sh, mask >> 32, mask);
     }
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -2082,7 +2118,7 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
     if (rA(ctx->opcode) == 0) {
         tcg_gen_movi_tl(cpu_T[0], simm);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         if (likely(simm != 0))
             gen_op_addi(simm);
     }
@@ -2094,10 +2130,10 @@ static always_inline void gen_addr_imm_index (DisasContext *ctx,
 static always_inline void gen_addr_reg_index (DisasContext *ctx)
 {
     if (rA(ctx->opcode) == 0) {
-        gen_op_load_gpr_T0(rB(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
-        gen_op_load_gpr_T1(rB(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
         gen_op_add();
     }
 #ifdef DEBUG_MEMORY_ACCESSES
@@ -2110,7 +2146,7 @@ static always_inline void gen_addr_register (DisasContext *ctx)
     if (rA(ctx->opcode) == 0) {
         tcg_gen_movi_tl(cpu_T[0], 0);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     }
 #ifdef DEBUG_MEMORY_ACCESSES
     gen_op_print_mem_EA();
@@ -2181,7 +2217,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type)                      \
 {                                                                             \
     gen_addr_imm_index(ctx, 0);                                               \
     op_ldst(l##width);                                                        \
-    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);                       \
 }
 
 #define GEN_LDU(width, opc, type)                                             \
@@ -2197,8 +2233,8 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
     else                                                                      \
         gen_addr_imm_index(ctx, 0);                                           \
     op_ldst(l##width);                                                        \
-    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);                       \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_LDUX(width, opc2, opc3, type)                                     \
@@ -2211,8 +2247,8 @@ GEN_HANDLER(l##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                 \
     }                                                                         \
     gen_addr_reg_index(ctx);                                                  \
     op_ldst(l##width);                                                        \
-    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);                       \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_LDX(width, opc2, opc3, type)                                      \
@@ -2220,7 +2256,7 @@ GEN_HANDLER(l##width##x, 0x1F, opc2, opc3, 0x00000001, type)                  \
 {                                                                             \
     gen_addr_reg_index(ctx);                                                  \
     op_ldst(l##width);                                                        \
-    gen_op_store_T1_gpr(rD(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);                       \
 }
 
 #define GEN_LDS(width, op, type)                                              \
@@ -2266,9 +2302,9 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
         /* ld - ldu */
         op_ldst(ld);
     }
-    gen_op_store_T1_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
     if (Rc(ctx->opcode))
-        gen_op_store_T0_gpr(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
 }
 /* lq */
 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
@@ -2296,10 +2332,10 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
     }
     gen_addr_imm_index(ctx, 0x0F);
     op_ldst(ld);
-    gen_op_store_T1_gpr(rd);
+    tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[1]);
     gen_op_addi(8);
     op_ldst(ld);
-    gen_op_store_T1_gpr(rd + 1);
+    tcg_gen_mov_tl(cpu_gpr[rd + 1], cpu_T[1]);
 #endif
 }
 #endif
@@ -2309,7 +2345,7 @@ GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX)
 GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type)                     \
 {                                                                             \
     gen_addr_imm_index(ctx, 0);                                               \
-    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);                       \
     op_ldst(st##width);                                                       \
 }
 
@@ -2324,9 +2360,9 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
         gen_addr_imm_index(ctx, 0x03);                                        \
     else                                                                      \
         gen_addr_imm_index(ctx, 0);                                           \
-    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);                       \
     op_ldst(st##width);                                                       \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_STUX(width, opc2, opc3, type)                                     \
@@ -2337,16 +2373,16 @@ GEN_HANDLER(st##width##ux, 0x1F, opc2, opc3, 0x00000001, type)                \
         return;                                                               \
     }                                                                         \
     gen_addr_reg_index(ctx);                                                  \
-    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);                       \
     op_ldst(st##width);                                                       \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_STX(width, opc2, opc3, type)                                      \
 GEN_HANDLER(st##width##x, 0x1F, opc2, opc3, 0x00000001, type)                 \
 {                                                                             \
     gen_addr_reg_index(ctx);                                                  \
-    gen_op_load_gpr_T1(rS(ctx->opcode));                                      \
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);                       \
     op_ldst(st##width);                                                       \
 }
 
@@ -2391,10 +2427,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
             return;
         }
         gen_addr_imm_index(ctx, 0x03);
-        gen_op_load_gpr_T1(rs);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
         op_ldst(std);
         gen_op_addi(8);
-        gen_op_load_gpr_T1(rs + 1);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs + 1]);
         op_ldst(std);
 #endif
     } else {
@@ -2406,10 +2442,10 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B)
             }
         }
         gen_addr_imm_index(ctx, 0x03);
-        gen_op_load_gpr_T1(rs);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rs]);
         op_ldst(std);
         if (Rc(ctx->opcode))
-            gen_op_store_T0_gpr(rA(ctx->opcode));
+            tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     }
 }
 #endif
@@ -2590,7 +2626,7 @@ GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000001, PPC_RES)
     gen_update_nip(ctx, ctx->nip - 4);
     gen_addr_reg_index(ctx);
     op_lwarx();
-    gen_op_store_T1_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
 }
 
 /* stwcx. */
@@ -2599,7 +2635,7 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES)
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
     gen_addr_reg_index(ctx);
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     op_stwcx();
 }
 
@@ -2620,7 +2656,7 @@ GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000001, PPC_64B)
     gen_update_nip(ctx, ctx->nip - 4);
     gen_addr_reg_index(ctx);
     op_ldarx();
-    gen_op_store_T1_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[1]);
 }
 
 /* stdcx. */
@@ -2629,7 +2665,7 @@ GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B)
     /* NIP cannot be restored if the memory exception comes from an helper */
     gen_update_nip(ctx, ctx->nip - 4);
     gen_addr_reg_index(ctx);
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     op_stdcx();
 }
 #endif /* defined(TARGET_PPC64) */
@@ -2674,7 +2710,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                   \
     gen_addr_imm_index(ctx, 0);                                               \
     op_ldst(l##width);                                                        \
     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_LDUXF(width, opc, type)                                           \
@@ -2691,7 +2727,7 @@ GEN_HANDLER(l##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                  \
     gen_addr_reg_index(ctx);                                                  \
     op_ldst(l##width);                                                        \
     gen_op_store_FT0_fpr(rD(ctx->opcode));                                    \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_LDXF(width, opc2, opc3, type)                                     \
@@ -2745,7 +2781,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type)                  \
     gen_addr_imm_index(ctx, 0);                                               \
     gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
     op_ldst(st##width);                                                       \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_STUXF(width, opc, type)                                           \
@@ -2762,7 +2798,7 @@ GEN_HANDLER(st##width##ux, 0x1F, 0x17, opc, 0x00000001, type)                 \
     gen_addr_reg_index(ctx);                                                  \
     gen_op_load_fpr_FT0(rS(ctx->opcode));                                     \
     op_ldst(st##width);                                                       \
-    gen_op_store_T0_gpr(rA(ctx->opcode));                                     \
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);                       \
 }
 
 #define GEN_STXF(width, opc2, opc3, type)                                     \
@@ -3154,8 +3190,8 @@ GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW)
 /* tw */
 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     /* Update the nip since this might generate a trap exception */
     gen_update_nip(ctx, ctx->nip);
     gen_op_tw(TO(ctx->opcode));
@@ -3164,7 +3200,7 @@ GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW)
 /* twi */
 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
     /* Update the nip since this might generate a trap exception */
     gen_update_nip(ctx, ctx->nip);
@@ -3175,8 +3211,8 @@ GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW)
 /* td */
 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     /* Update the nip since this might generate a trap exception */
     gen_update_nip(ctx, ctx->nip);
     gen_op_td(TO(ctx->opcode));
@@ -3185,7 +3221,7 @@ GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B)
 /* tdi */
 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
     /* Update the nip since this might generate a trap exception */
     gen_update_nip(ctx, ctx->nip);
@@ -3217,7 +3253,7 @@ GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC)
     } else {
         gen_op_load_cr();
     }
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 /* mfmsr */
@@ -3231,7 +3267,7 @@ GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC)
         return;
     }
     gen_op_load_msr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -3263,7 +3299,7 @@ static always_inline void gen_op_mfspr (DisasContext *ctx)
     if (likely(read_cb != NULL)) {
         if (likely(read_cb != SPR_NOACCESS)) {
             (*read_cb)(ctx, sprn);
-            gen_op_store_T0_gpr(rD(ctx->opcode));
+            tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
         } else {
             /* Privilege exception */
             /* This is a hack to avoid warnings when running Linux:
@@ -3309,7 +3345,7 @@ GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC)
 {
     uint32_t crm, crn;
 
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     crm = CRM(ctx->opcode);
     if (likely((ctx->opcode & 0x00100000) || (crm ^ (crm - 1)) == 0)) {
         crn = ffs(crm);
@@ -3332,7 +3368,7 @@ GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (ctx->opcode & 0x00010000) {
         /* Special form that does not need any synchronisation */
         gen_op_update_riee();
@@ -3360,7 +3396,7 @@ GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     if (ctx->opcode & 0x00010000) {
         /* Special form that does not need any synchronisation */
         gen_op_update_riee();
@@ -3399,7 +3435,7 @@ GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC)
         write_cb = ctx->spr_cb[sprn].uea_write;
     if (likely(write_cb != NULL)) {
         if (likely(write_cb != SPR_NOACCESS)) {
-            gen_op_load_gpr_T0(rS(ctx->opcode));
+            tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
             (*write_cb)(ctx, sprn);
         } else {
             /* Privilege exception */
@@ -3614,7 +3650,7 @@ GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT)
     }
     tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
     gen_op_load_sr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -3628,10 +3664,10 @@ GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_srli_T1(28);
     gen_op_load_sr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -3645,7 +3681,7 @@ GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
     gen_op_store_sr();
 #endif
@@ -3661,8 +3697,8 @@ GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_srli_T1(28);
     gen_op_store_sr();
 #endif
@@ -3682,7 +3718,7 @@ GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B)
     }
     tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
     gen_op_load_slb();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -3697,10 +3733,10 @@ GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_srli_T1(28);
     gen_op_load_slb();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -3714,7 +3750,7 @@ GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SR(ctx->opcode));
     gen_op_store_slb();
 #endif
@@ -3731,8 +3767,8 @@ GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_srli_T1(28);
     gen_op_store_slb();
 #endif
@@ -3765,7 +3801,7 @@ GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
 #if defined(TARGET_PPC64)
     if (ctx->sf_mode)
         gen_op_tlbie_64();
@@ -3817,7 +3853,7 @@ GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     gen_op_slbie();
 #endif
 }
@@ -3840,7 +3876,7 @@ GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN)
     /* Should check EAR[E] & alignment ! */
     gen_addr_reg_index(ctx);
     op_eciwx();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 /* ecowx */
@@ -3848,7 +3884,7 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
 {
     /* Should check EAR[E] & alignment ! */
     gen_addr_reg_index(ctx);
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     op_ecowx();
 }
 
@@ -3856,9 +3892,9 @@ GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN)
 /* abs - abs. */
 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_POWER_abs();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3866,9 +3902,9 @@ GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR)
 /* abso - abso. */
 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_POWER_abso();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3876,19 +3912,19 @@ GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR)
 /* clcs */
 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_POWER_clcs();
     /* Rc=1 sets CR0 to an undefined state */
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 /* div - div. */
 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_div();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3896,10 +3932,10 @@ GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR)
 /* divo - divo. */
 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_divo();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3907,10 +3943,10 @@ GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR)
 /* divs - divs. */
 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_divs();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3918,10 +3954,10 @@ GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR)
 /* divso - divso. */
 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_divso();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3929,10 +3965,10 @@ GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR)
 /* doz - doz. */
 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_doz();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3940,10 +3976,10 @@ GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR)
 /* dozo - dozo. */
 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_dozo();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -3951,10 +3987,10 @@ GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR)
 /* dozi */
 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SIMM(ctx->opcode));
     gen_op_POWER_doz();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 /* As lscbx load from memory byte after byte, it's always endian safe.
@@ -4001,10 +4037,10 @@ GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR)
 /* maskg - maskg. */
 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_maskg();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4012,11 +4048,11 @@ GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR)
 /* maskir - maskir. */
 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rS(ctx->opcode));
-    gen_op_load_gpr_T2(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_maskir();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4024,10 +4060,10 @@ GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR)
 /* mul - mul. */
 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_mul();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4035,10 +4071,10 @@ GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR)
 /* mulo - mulo. */
 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_mulo();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4046,9 +4082,9 @@ GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR)
 /* nabs - nabs. */
 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_POWER_nabs();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4056,9 +4092,9 @@ GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR)
 /* nabso - nabso. */
 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_POWER_nabso();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4070,11 +4106,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
 
     mb = MB(ctx->opcode);
     me = ME(ctx->opcode);
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rA(ctx->opcode));
-    gen_op_load_gpr_T2(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_rlmi(MASK(mb, me), ~MASK(mb, me));
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4082,11 +4118,11 @@ GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR)
 /* rrib - rrib. */
 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rA(ctx->opcode));
-    gen_op_load_gpr_T2(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_rrib();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4094,10 +4130,10 @@ GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR)
 /* sle - sle. */
 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sle();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4105,10 +4141,10 @@ GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR)
 /* sleq - sleq. */
 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sleq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4116,10 +4152,10 @@ GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR)
 /* sliq - sliq. */
 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
     gen_op_POWER_sle();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4127,10 +4163,10 @@ GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR)
 /* slliq - slliq. */
 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
     gen_op_POWER_sleq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4138,10 +4174,10 @@ GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR)
 /* sllq - sllq. */
 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sllq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4149,10 +4185,10 @@ GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR)
 /* slq - slq. */
 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_slq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4160,10 +4196,10 @@ GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR)
 /* sraiq - sraiq. */
 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
     gen_op_POWER_sraq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4171,10 +4207,10 @@ GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR)
 /* sraq - sraq. */
 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sraq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4182,10 +4218,10 @@ GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR)
 /* sre - sre. */
 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sre();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4193,10 +4229,10 @@ GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR)
 /* srea - srea. */
 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_srea();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4204,10 +4240,10 @@ GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR)
 /* sreq */
 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_sreq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4215,10 +4251,10 @@ GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR)
 /* sriq */
 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
     gen_op_POWER_srq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4226,11 +4262,11 @@ GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR)
 /* srliq */
 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     tcg_gen_movi_tl(cpu_T[1], SH(ctx->opcode));
     gen_op_POWER_srlq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4238,10 +4274,10 @@ GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR)
 /* srlq */
 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_srlq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4249,10 +4285,10 @@ GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR)
 /* srq */
 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_POWER_srq();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     if (unlikely(Rc(ctx->opcode) != 0))
         gen_set_Rc0(ctx);
 }
@@ -4282,9 +4318,9 @@ GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_602_mfrom();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -4299,7 +4335,7 @@ GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     gen_op_6xx_tlbld();
 #endif
 }
@@ -4314,7 +4350,7 @@ GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     gen_op_6xx_tlbli();
 #endif
 }
@@ -4330,7 +4366,7 @@ GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     gen_op_74xx_tlbld();
 #endif
 }
@@ -4345,7 +4381,7 @@ GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rB(ctx->opcode)]);
     gen_op_74xx_tlbli();
 #endif
 }
@@ -4391,9 +4427,9 @@ GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER)
 
     gen_addr_reg_index(ctx);
     gen_op_POWER_mfsri();
-    gen_op_store_T0_gpr(rd);
+    tcg_gen_mov_tl(cpu_gpr[rd], cpu_T[0]);
     if (ra != 0 && ra != rd)
-        gen_op_store_T1_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[1]);
 #endif
 }
 
@@ -4408,7 +4444,7 @@ GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER)
     }
     gen_addr_reg_index(ctx);
     gen_op_POWER_rac();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -4479,7 +4515,7 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
     gen_op_store_FT0_fpr(rD(ctx->opcode));
     gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
     if (ra != 0)
-        gen_op_store_T0_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
 }
 
 /* lfqux */
@@ -4494,7 +4530,7 @@ GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2)
     gen_op_store_FT0_fpr(rD(ctx->opcode));
     gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
     if (ra != 0)
-        gen_op_store_T0_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
 }
 
 /* lfqx */
@@ -4531,7 +4567,7 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
     gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
     op_POWER2_stfq();
     if (ra != 0)
-        gen_op_store_T0_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
 }
 
 /* stfqux */
@@ -4546,7 +4582,7 @@ GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2)
     gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
     op_POWER2_stfq();
     if (ra != 0)
-        gen_op_store_T0_gpr(ra);
+        tcg_gen_mov_tl(cpu_gpr[ra], cpu_T[0]);
 }
 
 /* stfqx */
@@ -4594,8 +4630,8 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
                                                 int opc2, int opc3,
                                                 int ra, int rb, int rt, int Rc)
 {
-    gen_op_load_gpr_T0(ra);
-    gen_op_load_gpr_T1(rb);
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[ra]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rb]);
     switch (opc3 & 0x0D) {
     case 0x05:
         /* macchw    - macchw.    - macchwo   - macchwo.   */
@@ -4646,7 +4682,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
     }
     if (opc2 & 0x04) {
         /* (n)multiply-and-accumulate (0x0C - 0x0E) */
-        gen_op_load_gpr_T2(rt);
+        tcg_gen_mov_tl(cpu_T[2], cpu_gpr[rt]);
         tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
         gen_op_405_add_T0_T2();
     }
@@ -4664,7 +4700,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
         else
             gen_op_405_check_satu();
     }
-    gen_op_store_T0_gpr(rt);
+    tcg_gen_mov_tl(cpu_gpr[rt], cpu_T[0]);
     if (unlikely(Rc) != 0) {
         /* Update Rc0 */
         gen_set_Rc0(ctx);
@@ -4778,7 +4814,7 @@ GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR)
     }
     tcg_gen_movi_tl(cpu_T[0], dcrn);
     gen_op_load_dcr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -4795,7 +4831,7 @@ GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR)
         return;
     }
     tcg_gen_movi_tl(cpu_T[0], dcrn);
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     gen_op_store_dcr();
 #endif
 }
@@ -4811,9 +4847,9 @@ GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_load_dcr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     /* Note: Rc update flag set leads to undefined state of Rc0 */
 #endif
 }
@@ -4829,8 +4865,8 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
         GEN_EXCP_PRIVREG(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     gen_op_store_dcr();
     /* Note: Rc update flag set leads to undefined state of Rc0 */
 #endif
@@ -4839,17 +4875,17 @@ GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX)
 /* mfdcrux (PPC 460) : user-mode access to DCR */
 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
     gen_op_load_dcr();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
     /* Note: Rc update flag set leads to undefined state of Rc0 */
 }
 
 /* mtdcrux (PPC 460) : user-mode access to DCR */
 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX)
 {
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rS(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
     gen_op_store_dcr();
     /* Note: Rc update flag set leads to undefined state of Rc0 */
 }
@@ -4880,7 +4916,7 @@ GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON)
     }
     gen_addr_reg_index(ctx);
     op_ldst(lwz);
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -4998,14 +5034,14 @@ GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB)
     }
     switch (rB(ctx->opcode)) {
     case 0:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         gen_op_4xx_tlbre_hi();
-        gen_op_store_T0_gpr(rD(ctx->opcode));
+        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
         break;
     case 1:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         gen_op_4xx_tlbre_lo();
-        gen_op_store_T0_gpr(rD(ctx->opcode));
+        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
         break;
     default:
         GEN_EXCP_INVAL(ctx);
@@ -5028,7 +5064,7 @@ GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB)
     gen_op_4xx_tlbsx();
     if (Rc(ctx->opcode))
         gen_op_4xx_tlbsx_check();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -5044,13 +5080,13 @@ GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB)
     }
     switch (rB(ctx->opcode)) {
     case 0:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
-        gen_op_load_gpr_T1(rS(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
         gen_op_4xx_tlbwe_hi();
         break;
     case 1:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
-        gen_op_load_gpr_T1(rS(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
         gen_op_4xx_tlbwe_lo();
         break;
     default:
@@ -5075,9 +5111,9 @@ GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE)
     case 0:
     case 1:
     case 2:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         gen_op_440_tlbre(rB(ctx->opcode));
-        gen_op_store_T0_gpr(rD(ctx->opcode));
+        tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
         break;
     default:
         GEN_EXCP_INVAL(ctx);
@@ -5100,7 +5136,7 @@ GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE)
     gen_op_440_tlbsx();
     if (Rc(ctx->opcode))
         gen_op_4xx_tlbsx_check();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 #endif
 }
 
@@ -5118,8 +5154,8 @@ GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE)
     case 0:
     case 1:
     case 2:
-        gen_op_load_gpr_T0(rA(ctx->opcode));
-        gen_op_load_gpr_T1(rS(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+        tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rS(ctx->opcode)]);
         gen_op_440_tlbwe(rB(ctx->opcode));
         break;
     default:
@@ -5139,7 +5175,7 @@ GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE)
         GEN_EXCP_PRIVOPC(ctx);
         return;
     }
-    gen_op_load_gpr_T0(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rD(ctx->opcode)]);
     gen_op_wrte();
     /* Stop translation to have a chance to raise an exception
      * if we just set msr_ee to 1
@@ -5171,10 +5207,10 @@ GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000EFC01, PPC_WRTEE)
 /* dlmzb */
 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC)
 {
-    gen_op_load_gpr_T0(rS(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rS(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_440_dlmzb();
-    gen_op_store_T0_gpr(rA(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_T[0]);
     gen_op_store_xer_bc();
     if (Rc(ctx->opcode)) {
         gen_op_440_dlmzb_update_Rc();
@@ -5263,36 +5299,31 @@ GEN_VR_STX(vxl, 0x07, 0x0F);
 
 /***                           SPE extension                               ***/
 /* Register moves */
-#if !defined(TARGET_PPC64)
 
-GEN32(gen_op_load_gpr64_T0, gen_op_load_gpr64_T0_gpr);
-GEN32(gen_op_load_gpr64_T1, gen_op_load_gpr64_T1_gpr);
-#if 0 // unused
-GEN32(gen_op_load_gpr64_T2, gen_op_load_gpr64_T2_gpr);
+static always_inline void gen_load_gpr64(TCGv t, int reg) {
+#if defined(TARGET_PPC64)
+    tcg_gen_mov_i64(t, cpu_gpr[reg]);
+#else
+    tcg_gen_extu_i32_i64(t, cpu_gprh[reg]);
+    tcg_gen_shli_i64(t, t, 32);
+    TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
+    tcg_gen_extu_i32_i64(tmp, cpu_gpr[reg]);
+    tcg_gen_or_i64(t, t, tmp);
+    tcg_temp_free(tmp);
 #endif
+}
 
-GEN32(gen_op_store_T0_gpr64, gen_op_store_T0_gpr64_gpr);
-GEN32(gen_op_store_T1_gpr64, gen_op_store_T1_gpr64_gpr);
-#if 0 // unused
-GEN32(gen_op_store_T2_gpr64, gen_op_store_T2_gpr64_gpr);
+static always_inline void gen_store_gpr64(int reg, TCGv t) {
+#if defined(TARGET_PPC64)
+    tcg_gen_mov_i64(cpu_gpr[reg], t);
+#else
+    tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
+    TCGv tmp = tcg_temp_local_new(TCG_TYPE_I64);
+    tcg_gen_shri_i64(tmp, t, 32);
+    tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
+    tcg_temp_free(tmp);
 #endif
-
-#else /* !defined(TARGET_PPC64) */
-
-/* No specific load/store functions: GPRs are already 64 bits */
-#define gen_op_load_gpr64_T0 gen_op_load_gpr_T0
-#define gen_op_load_gpr64_T1 gen_op_load_gpr_T1
-#if 0 // unused
-#define gen_op_load_gpr64_T2 gen_op_load_gpr_T2
-#endif
-
-#define gen_op_store_T0_gpr64 gen_op_store_T0_gpr
-#define gen_op_store_T1_gpr64 gen_op_store_T1_gpr
-#if 0 // unused
-#define gen_op_store_T2_gpr64 gen_op_store_T2_gpr
-#endif
-
-#endif /* !defined(TARGET_PPC64) */
+}
 
 #define GEN_SPE(name0, name1, opc2, opc3, inval, type)                        \
 GEN_HANDLER(name0##_##name1, 0x04, opc2, opc3, inval, type)                   \
@@ -5317,7 +5348,7 @@ static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, int sh)
     if (rA(ctx->opcode) == 0) {
         tcg_gen_movi_tl(cpu_T[0], simm << sh);
     } else {
-        gen_op_load_gpr_T0(rA(ctx->opcode));
+        tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
         if (likely(simm != 0))
             gen_op_addi(simm << sh);
     }
@@ -5342,7 +5373,7 @@ static always_inline void gen_evl##name (DisasContext *ctx)                   \
     }                                                                         \
     gen_addr_spe_imm_index(ctx, sh);                                          \
     op_spe_ldst(spe_l##name);                                                 \
-    gen_op_store_T1_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]);                             \
 }
 
 #define GEN_SPE_LDX(name)                                                     \
@@ -5354,7 +5385,7 @@ static always_inline void gen_evl##name##x (DisasContext *ctx)                \
     }                                                                         \
     gen_addr_reg_index(ctx);                                                  \
     op_spe_ldst(spe_l##name);                                                 \
-    gen_op_store_T1_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[1]);                             \
 }
 
 #define GEN_SPEOP_LD(name, sh)                                                \
@@ -5370,7 +5401,7 @@ static always_inline void gen_evst##name (DisasContext *ctx)                  \
         return;                                                               \
     }                                                                         \
     gen_addr_spe_imm_index(ctx, sh);                                          \
-    gen_op_load_gpr64_T1(rS(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[1], rS(ctx->opcode));                              \
     op_spe_ldst(spe_st##name);                                                \
 }
 
@@ -5382,7 +5413,7 @@ static always_inline void gen_evst##name##x (DisasContext *ctx)               \
         return;                                                               \
     }                                                                         \
     gen_addr_reg_index(ctx);                                                  \
-    gen_op_load_gpr64_T1(rS(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[1], rS(ctx->opcode));                              \
     op_spe_ldst(spe_st##name);                                                \
 }
 
@@ -5403,10 +5434,10 @@ static always_inline void gen_##name (DisasContext *ctx)                      \
         GEN_EXCP_NO_AP(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
-    gen_op_load_gpr64_T1(rB(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));                              \
+    gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));                              \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
 }
 
 #define GEN_SPEOP_ARITH1(name)                                                \
@@ -5416,9 +5447,9 @@ static always_inline void gen_##name (DisasContext *ctx)                      \
         GEN_EXCP_NO_AP(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));                              \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
 }
 
 #define GEN_SPEOP_COMP(name)                                                  \
@@ -5428,8 +5459,8 @@ static always_inline void gen_##name (DisasContext *ctx)                      \
         GEN_EXCP_NO_AP(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
-    gen_op_load_gpr64_T1(rB(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));                              \
+    gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));                              \
     gen_op_##name();                                                          \
     gen_op_store_T0_crf(crfD(ctx->opcode));                                   \
 }
@@ -5465,10 +5496,10 @@ GEN_SPEOP_ARITH1(evcntlsw);
 static always_inline void gen_brinc (DisasContext *ctx)
 {
     /* Note: brinc is usable even if SPE is disabled */
-    gen_op_load_gpr_T0(rA(ctx->opcode));
-    gen_op_load_gpr_T1(rB(ctx->opcode));
+    tcg_gen_mov_tl(cpu_T[0], cpu_gpr[rA(ctx->opcode)]);
+    tcg_gen_mov_tl(cpu_T[1], cpu_gpr[rB(ctx->opcode)]);
     gen_op_brinc();
-    gen_op_store_T0_gpr(rD(ctx->opcode));
+    tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_T[0]);
 }
 
 #define GEN_SPEOP_ARITH_IMM2(name)                                            \
@@ -5478,10 +5509,10 @@ static always_inline void gen_##name##i (DisasContext *ctx)                   \
         GEN_EXCP_NO_AP(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    gen_op_load_gpr64_T0(rB(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rB(ctx->opcode));                              \
     gen_op_splatwi_T1_64(rA(ctx->opcode));                                    \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
 }
 
 #define GEN_SPEOP_LOGIC_IMM2(name)                                            \
@@ -5491,10 +5522,10 @@ static always_inline void gen_##name##i (DisasContext *ctx)                   \
         GEN_EXCP_NO_AP(ctx);                                                  \
         return;                                                               \
     }                                                                         \
-    gen_op_load_gpr64_T0(rA(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));                              \
     gen_op_splatwi_T1_64(rB(ctx->opcode));                                    \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
 }
 
 GEN_SPEOP_ARITH_IMM2(evaddw);
@@ -5513,7 +5544,7 @@ static always_inline void gen_evsplati (DisasContext *ctx)
     int32_t imm = (int32_t)(rA(ctx->opcode) << 27) >> 27;
 
     gen_op_splatwi_T0_64(imm);
-    gen_op_store_T0_gpr64(rD(ctx->opcode));
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
 }
 
 static always_inline void gen_evsplatfi (DisasContext *ctx)
@@ -5521,7 +5552,7 @@ static always_inline void gen_evsplatfi (DisasContext *ctx)
     uint32_t imm = rA(ctx->opcode) << 27;
 
     gen_op_splatwi_T0_64(imm);
-    gen_op_store_T0_gpr64(rD(ctx->opcode));
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
 }
 
 /* Comparison */
@@ -5564,10 +5595,10 @@ static always_inline void gen_evsel (DisasContext *ctx)
         return;
     }
     gen_op_load_crf_T0(ctx->opcode & 0x7);
-    gen_op_load_gpr64_T0(rA(ctx->opcode));
-    gen_op_load_gpr64_T1(rB(ctx->opcode));
+    gen_load_gpr64(cpu_T64[0], rA(ctx->opcode));
+    gen_load_gpr64(cpu_T64[1], rB(ctx->opcode));
     gen_op_evsel();
-    gen_op_store_T0_gpr64(rD(ctx->opcode));
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);
 }
 
 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE)
@@ -5906,9 +5937,9 @@ GEN_SPE(speundef,       evmwsmfan,     0x0D, 0x17, 0x00000000, PPC_SPE);
 #define GEN_SPEFPUOP_CONV(name)                                               \
 static always_inline void gen_##name (DisasContext *ctx)                      \
 {                                                                             \
-    gen_op_load_gpr64_T0(rB(ctx->opcode));                                    \
+    gen_load_gpr64(cpu_T64[0], rB(ctx->opcode));                              \
     gen_op_##name();                                                          \
-    gen_op_store_T0_gpr64(rD(ctx->opcode));                                   \
+    gen_store_gpr64(rD(ctx->opcode), cpu_T64[0]);                             \
 }
 
 /* Single precision floating-point vectors operations */