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Better STOPINTR bit semantics in the PXA2xx DMA. 

Don't error out on reading GPCR register, just warn (Thorsten Zitterell).
Don't zero a memory that's already zeroed.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3676 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2007-11-17 18:43:47 +00:00
parent 749bc4bf0b
commit e1dad5a615
4 changed files with 9 additions and 3 deletions
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4
hw/pxa2xx_dma.c
View File

@ -348,8 +348,10 @@ static void pxa2xx_dma_write(void *opaque,
if (value & DCSR_NODESCFETCH) {
/* No-descriptor-fetch mode */
if (value & DCSR_RUN)
if (value & DCSR_RUN) {
s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_run(s);
}
} else {
/* Descriptor-fetch mode */
if (value & DCSR_RUN) {

5
hw/pxa2xx_gpio.c
View File

@ -154,6 +154,11 @@ static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
__FUNCTION__, offset);
return s->gpsr[bank]; /* Return last written value. */
case GPCR: /* GPIO Pin-Output Clear registers */
printf("%s: Read from a write-only register " REG_FMT "\n",
__FUNCTION__, offset);
return 31337; /* Specified as unpredictable in the docs. */
case GRER: /* GPIO Rising-Edge Detect Enable registers */
return s->rising[bank];

2
hw/pxa2xx_mmci.c
View File

@ -549,5 +549,5 @@ struct pxa2xx_mmci_s *pxa2xx_mmci_init(target_phys_addr_t base,
void pxa2xx_mmci_handlers(struct pxa2xx_mmci_s *s, qemu_irq readonly,
qemu_irq coverswitch)
{
sd_set_cb(s->card, read, coverswitch);
sd_set_cb(s->card, readonly, coverswitch);
}

1
hw/sd.c
View File

@ -377,7 +377,6 @@ static void sd_reset(SDState *sd, BlockDriverState *bdrv)
qemu_free(sd->wp_groups);
sd->wp_switch = bdrv_is_read_only(bdrv);
sd->wp_groups = (int *) qemu_mallocz(sizeof(int) * sect);
memset(sd->wp_groups, 0, sizeof(int) * sect);
memset(sd->function_group, 0, sizeof(int) * 6);
sd->erase_start = 0;
sd->erase_end = 0;