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qemu
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Merge remote-tracking branch 'qemu-kvm-tmp/memory/batch' into staging

This commit is contained in:
Anthony Liguori 2011-09-08 09:03:57 -05:00
parent 9d0baba110 c50a6def96
commit d8ac46d950
47 changed files with 550 additions and 593 deletions
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1
Makefile.hw
View File

@ -10,6 +10,7 @@ include $(SRC_PATH)/rules.mak
$(call set-vpath, $(SRC_PATH):$(SRC_PATH)/hw)
QEMU_CFLAGS+=-I..
QEMU_CFLAGS += $(GLIB_CFLAGS)
include $(SRC_PATH)/Makefile.objs

1
Makefile.target
View File

@ -191,7 +191,6 @@ obj-$(CONFIG_VIRTIO) += virtio.o virtio-blk.o virtio-balloon.o virtio-net.o virt
obj-y += vhost_net.o
obj-$(CONFIG_VHOST_NET) += vhost.o
obj-$(CONFIG_REALLY_VIRTFS) += 9pfs/virtio-9p-device.o
obj-y += rwhandler.o
obj-$(CONFIG_KVM) += kvm.o kvm-all.o
obj-$(CONFIG_NO_KVM) += kvm-stub.o
obj-y += memory.o

12
hw/an5206.c
View File

@ -12,6 +12,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
#define AN5206_MBAR_ADDR 0x10000000
@ -37,6 +38,9 @@ static void an5206_init(ram_addr_t ram_size,
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5206";
@ -52,12 +56,12 @@ static void an5206_init(ram_addr_t ram_size,
env->rambar0 = AN5206_RAMBAR_ADDR | 1;
/* DRAM at address zero */
cpu_register_physical_memory(0, ram_size,
qemu_ram_alloc(NULL, "an5206.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "an5206.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Internal SRAM. */
cpu_register_physical_memory(AN5206_RAMBAR_ADDR, 512,
qemu_ram_alloc(NULL, "an5206.sram", 512) | IO_MEM_RAM);
memory_region_init_ram(sram, NULL, "an5206.sram", 512);
memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram);
mcf5206_init(AN5206_MBAR_ADDR, env);

5
hw/arm-misc.h
View File

@ -11,13 +11,16 @@
#ifndef ARM_MISC_H
#define ARM_MISC_H 1
#include "memory.h"
/* The CPU is also modeled as an interrupt controller. */
#define ARM_PIC_CPU_IRQ 0
#define ARM_PIC_CPU_FIQ 1
qemu_irq *arm_pic_init_cpu(CPUState *env);
/* armv7m.c */
qemu_irq *armv7m_init(int flash_size, int sram_size,
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model);
/* arm_boot.c */

22
hw/armv7m.c
View File

@ -156,7 +156,8 @@ static void armv7m_reset(void *opaque)
flash_size and sram_size are in kb.
Returns the NVIC array. */
qemu_irq *armv7m_init(int flash_size, int sram_size,
qemu_irq *armv7m_init(MemoryRegion *address_space_mem,
int flash_size, int sram_size,
const char *kernel_filename, const char *cpu_model)
{
CPUState *env;
@ -169,6 +170,9 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
uint64_t lowaddr;
int i;
int big_endian;
MemoryRegion *sram = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *hack = g_new(MemoryRegion, 1);
flash_size *= 1024;
sram_size *= 1024;
@ -194,12 +198,11 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
#endif
/* Flash programming is done via the SCU, so pretend it is ROM. */
cpu_register_physical_memory(0, flash_size,
qemu_ram_alloc(NULL, "armv7m.flash",
flash_size) | IO_MEM_ROM);
cpu_register_physical_memory(0x20000000, sram_size,
qemu_ram_alloc(NULL, "armv7m.sram",
sram_size) | IO_MEM_RAM);
memory_region_init_ram(flash, NULL, "armv7m.flash", flash_size);
memory_region_set_readonly(flash, true);
memory_region_add_subregion(address_space_mem, 0, flash);
memory_region_init_ram(sram, NULL, "armv7m.sram", sram_size);
memory_region_add_subregion(address_space_mem, 0x20000000, sram);
armv7m_bitband_init();
nvic = qdev_create(NULL, "armv7m_nvic");
@ -232,9 +235,8 @@ qemu_irq *armv7m_init(int flash_size, int sram_size,
/* Hack to map an additional page of ram at the top of the address
space. This stops qemu complaining about executing code outside RAM
when returning from an exception. */
cpu_register_physical_memory(0xfffff000, 0x1000,
qemu_ram_alloc(NULL, "armv7m.hack",
0x1000) | IO_MEM_RAM);
memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000);
memory_region_add_subregion(address_space_mem, 0xfffff000, hack);
qemu_register_reset(armv7m_reset, env);
return pic;

16
hw/axis_dev88.c
View File

@ -31,6 +31,7 @@
#include "elf.h"
#include "cris-boot.h"
#include "blockdev.h"
#include "exec-memory.h"
#define D(x)
#define DNAND(x)
@ -259,8 +260,9 @@ void axisdev88_init (ram_addr_t ram_size,
int i;
int nand_regs;
int gpio_regs;
ram_addr_t phys_ram;
ram_addr_t phys_intmem;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
MemoryRegion *phys_intmem = g_new(MemoryRegion, 1);
/* init CPUs */
if (cpu_model == NULL) {
@ -269,15 +271,13 @@ void axisdev88_init (ram_addr_t ram_size,
env = cpu_init(cpu_model);
/* allocate RAM */
phys_ram = qemu_ram_alloc(NULL, "axisdev88.ram", ram_size);
cpu_register_physical_memory(0x40000000, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "axisdev88.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, phys_ram);
/* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the
internal memory. */
phys_intmem = qemu_ram_alloc(NULL, "axisdev88.chipram", INTMEM_SIZE);
cpu_register_physical_memory(0x38000000, INTMEM_SIZE,
phys_intmem | IO_MEM_RAM);
memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE);
memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem);
/* Attach a NAND flash to CS1. */
nand = drive_get(IF_MTD, 0, 0);

2
hw/cirrus_vga.c
View File

@ -2424,6 +2424,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
{
unsigned mode;
memory_region_transaction_begin();
if ((s->vga.sr[0x17] & 0x44) == 0x44) {
goto generic_io;
} else if (s->cirrus_srcptr != s->cirrus_srcptr_end) {
@ -2443,6 +2444,7 @@ static void cirrus_update_memory_access(CirrusVGAState *s)
unmap_linear_vram(s);
}
}
memory_region_transaction_commit();
}

7
hw/collie.c
View File

@ -26,7 +26,6 @@ static void collie_init(ram_addr_t ram_size,
{
StrongARMState *s;
DriveInfo *dinfo;
ram_addr_t phys_flash;
if (!cpu_model) {
cpu_model = "sa1110";
@ -34,15 +33,13 @@ static void collie_init(ram_addr_t ram_size,
s = sa1110_init(collie_binfo.ram_size, cpu_model);
phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, phys_flash,
pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0);
phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, phys_flash,
pflash_cfi01_register(SA_CS1, NULL, "collie.fl2", 0x02000000,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0);

13
hw/dec_pci.c
View File

@ -80,16 +80,15 @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
static int pci_dec_21154_init_device(SysBusDevice *dev)
{
DECState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(DECState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}

7
hw/dummy_m68k.c
View File

@ -10,6 +10,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define KERNEL_LOAD_ADDR 0x10000
@ -21,6 +22,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
int kernel_size;
uint64_t elf_entry;
target_phys_addr_t entry;
@ -37,8 +40,8 @@ static void dummy_m68k_init(ram_addr_t ram_size,
env->vbr = 0;
/* RAM at address zero */
cpu_register_physical_memory(0, ram_size,
qemu_ram_alloc(NULL, "dummy_m68k.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "dummy_m68k.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0, ram);
/* Load kernel. */
if (kernel_filename) {

13
hw/flash.h
View File

@ -1,15 +1,22 @@
/* NOR flash devices */
#include "memory.h"
typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pflash_t *pflash_cfi01_register(target_phys_addr_t base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be);
/* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
pflash_t *pflash_cfi02_register(target_phys_addr_t base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
@ -17,6 +24,8 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
uint16_t unlock_addr0, uint16_t unlock_addr1,
int be);
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl);
/* nand.c */
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);
void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,

13
hw/grackle_pci.c
View File

@ -92,16 +92,15 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic,
static int pci_grackle_init_device(SysBusDevice *dev)
{
GrackleState *s;
int pci_mem_config, pci_mem_data;
s = FROM_SYSBUS(GrackleState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-data-idx", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_grackle_reset, &s->host_state);
return 0;

6
hw/gumstix.c
View File

@ -67,8 +67,7 @@ static void connex_init(ram_addr_t ram_size,
#else
be = 0;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom",
connex_rom),
if (!pflash_cfi01_register(0x00000000, NULL, "connext.rom", connex_rom,
dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");
@ -106,8 +105,7 @@ static void verdex_init(ram_addr_t ram_size,
#else
be = 0;
#endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom",
verdex_rom),
if (!pflash_cfi01_register(0x00000000, NULL, "verdex.rom", verdex_rom,
dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0, be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n");

28
hw/integratorcp.c
View File

@ -13,11 +13,13 @@
#include "boards.h"
#include "arm-misc.h"
#include "net.h"
#include "exec-memory.h"
typedef struct {
SysBusDevice busdev;
uint32_t memsz;
uint32_t flash_offset;
MemoryRegion flash;
bool flash_mapped;
uint32_t cm_osc;
uint32_t cm_ctrl;
uint32_t cm_lock;
@ -108,9 +110,15 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset)
static void integratorcm_do_remap(integratorcm_state *s, int flash)
{
if (flash) {
cpu_register_physical_memory(0, 0x100000, IO_MEM_RAM);
if (s->flash_mapped) {
sysbus_del_memory(&s->busdev, &s->flash);
s->flash_mapped = false;
}
} else {
cpu_register_physical_memory(0, 0x100000, s->flash_offset | IO_MEM_RAM);
if (!s->flash_mapped) {
sysbus_add_memory_overlap(&s->busdev, 0, &s->flash, 1);
s->flash_mapped = true;
}
}
//??? tlb_flush (cpu_single_env, 1);
}
@ -252,7 +260,8 @@ static int integratorcm_init(SysBusDevice *dev)
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
memory_region_init_ram(&s->flash, NULL, "integrator.flash", 0x100000);
s->flash_mapped = false;
iomemtype = cpu_register_io_memory(integratorcm_readfn,
integratorcm_writefn, s,
@ -456,7 +465,9 @@ static void integratorcp_init(ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *ram_alias = g_new(MemoryRegion, 1);
qemu_irq pic[32];
qemu_irq *cpu_pic;
DeviceState *dev;
@ -469,13 +480,14 @@ static void integratorcp_init(ram_addr_t ram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
memory_region_init_ram(ram, NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
memory_region_add_subregion(address_space_mem, 0, ram);
/* And again at address 0x80000000 */
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_alias(ram_alias, "ram.alias", ram, 0, ram_size);
memory_region_add_subregion(address_space_mem, 0x80000000, ram_alias);
dev = qdev_create(NULL, "integrator_core");
qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);

15
hw/leon3.c
View File

@ -29,6 +29,7 @@
#include "loader.h"
#include "elf.h"
#include "trace.h"
#include "exec-memory.h"
#include "grlib.h"
@ -100,7 +101,9 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset, prom_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *prom = g_new(MemoryRegion, 1);
int ret;
char *filename;
qemu_irq *cpu_irqs = NULL;
@ -139,14 +142,14 @@ static void leon3_generic_hw_init(ram_addr_t ram_size,
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "leon3.ram", ram_size);
cpu_register_physical_memory(0x40000000, ram_size, ram_offset | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "leon3.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Allocate BIOS */
prom_size = 8 * 1024 * 1024; /* 8Mb */
prom_offset = qemu_ram_alloc(NULL, "Leon3.bios", prom_size);
cpu_register_physical_memory(0x00000000, prom_size,
prom_offset | IO_MEM_ROM);
memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size);
memory_region_set_readonly(prom, true);
memory_region_add_subregion(address_space_mem, 0x00000000, prom);
/* Load boot prom */
if (bios_name == NULL) {

23
hw/lm32_boards.c
View File

@ -28,6 +28,7 @@
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec-memory.h"
typedef struct {
CPUState *env;
@ -76,8 +77,8 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info;
int i;
@ -105,13 +106,12 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "lm32_evr.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
@ -164,8 +164,8 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
{
CPUState *env;
DriveInfo *dinfo;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32];
HWSetup *hw;
ResetInfo *reset_info;
@ -200,13 +200,12 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
reset_info->flash_base = flash_base;
phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
memory_region_init_ram(phys_ram, NULL, "lm32_uclinux.sdram", ram_size);
memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash,
pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

20
hw/mainstone.c
View File

@ -17,6 +17,7 @@
#include "flash.h"
#include "blockdev.h"
#include "sysbus.h"
#include "exec-memory.h"
/* Device addresses */
#define MST_FPGA_PHYS 0x08000000
@ -90,7 +91,8 @@ static struct arm_boot_info mainstone_binfo = {
.ram_size = 0x04000000,
};
static void mainstone_common_init(ram_addr_t ram_size,
static void mainstone_common_init(MemoryRegion *address_space_mem,
ram_addr_t ram_size,
const char *kernel_filename,
const char *kernel_cmdline, const char *initrd_filename,
const char *cpu_model, enum mainstone_model_e model, int arm_id)
@ -102,15 +104,16 @@ static void mainstone_common_init(ram_addr_t ram_size,
DriveInfo *dinfo;
int i;
int be;
MemoryRegion *rom = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "pxa270-c5";
/* Setup CPU & memory */
cpu = pxa270_init(mainstone_binfo.ram_size, cpu_model);
cpu_register_physical_memory(0, MAINSTONE_ROM,
qemu_ram_alloc(NULL, "mainstone.rom",
MAINSTONE_ROM) | IO_MEM_ROM);
memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM);
memory_region_set_readonly(rom, true);
memory_region_add_subregion(address_space_mem, 0, rom);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
@ -126,10 +129,9 @@ static void mainstone_common_init(ram_addr_t ram_size,
exit(1);
}
if (!pflash_cfi01_register(mainstone_flash_base[i],
qemu_ram_alloc(NULL, i ? "mainstone.flash1" :
"mainstone.flash0",
MAINSTONE_FLASH),
if (!pflash_cfi01_register(mainstone_flash_base[i], NULL,
i ? "mainstone.flash1" : "mainstone.flash0",
MAINSTONE_FLASH,
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
@ -170,7 +172,7 @@ static void mainstone_init(ram_addr_t ram_size,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
mainstone_common_init(ram_size, kernel_filename,
mainstone_common_init(get_system_memory(), ram_size, kernel_filename,
kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196);
}

72
hw/mcf5208.c
View File

@ -13,6 +13,7 @@
#include "boards.h"
#include "loader.h"
#include "elf.h"
#include "exec-memory.h"
#define SYS_FREQ 66000000
@ -27,6 +28,7 @@
#define PCSR_PRE_MASK 0x0f00
typedef struct {
MemoryRegion iomem;
qemu_irq irq;
ptimer_state *timer;
uint16_t pcsr;
@ -43,7 +45,7 @@ static void m5208_timer_update(m5208_timer_state *s)
}
static void m5208_timer_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
int prescale;
@ -104,7 +106,8 @@ static void m5208_timer_trigger(void *opaque)
m5208_timer_update(s);
}
static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
static uint64_t m5208_timer_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
m5208_timer_state *s = (m5208_timer_state *)opaque;
switch (addr) {
@ -120,19 +123,14 @@ static uint32_t m5208_timer_read(void *opaque, target_phys_addr_t addr)
}
}
static CPUReadMemoryFunc * const m5208_timer_readfn[] = {
m5208_timer_read,
m5208_timer_read,
m5208_timer_read
static const MemoryRegionOps m5208_timer_ops = {
.read = m5208_timer_read,
.write = m5208_timer_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const m5208_timer_writefn[] = {
m5208_timer_write,
m5208_timer_write,
m5208_timer_write
};
static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
static uint64_t m5208_sys_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
switch (addr) {
case 0x110: /* SDCS0 */
@ -154,45 +152,36 @@ static uint32_t m5208_sys_read(void *opaque, target_phys_addr_t addr)
}
static void m5208_sys_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
uint64_t value, unsigned size)
{
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
}
static CPUReadMemoryFunc * const m5208_sys_readfn[] = {
m5208_sys_read,
m5208_sys_read,
m5208_sys_read
static const MemoryRegionOps m5208_sys_ops = {
.read = m5208_sys_read,
.write = m5208_sys_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const m5208_sys_writefn[] = {
m5208_sys_write,
m5208_sys_write,
m5208_sys_write
};
static void mcf5208_sys_init(qemu_irq *pic)
static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
{
int iomemtype;
MemoryRegion *iomem = g_new(MemoryRegion, 1);
m5208_timer_state *s;
QEMUBH *bh;
int i;
iomemtype = cpu_register_io_memory(m5208_sys_readfn,
m5208_sys_writefn, NULL,
DEVICE_NATIVE_ENDIAN);
/* SDRAMC. */
cpu_register_physical_memory(0xfc0a8000, 0x00004000, iomemtype);
memory_region_init_io(iomem, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
/* Timers. */
for (i = 0; i < 2; i++) {
s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
bh = qemu_bh_new(m5208_timer_trigger, s);
s->timer = ptimer_init(bh);
iomemtype = cpu_register_io_memory(m5208_timer_readfn,
m5208_timer_writefn, s,
DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(0xfc080000 + 0x4000 * i, 0x00004000,
iomemtype);
memory_region_init_io(&s->iomem, &m5208_timer_ops, s,
"m5208-timer", 0x00004000);
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
&s->iomem);
s->irq = pic[4 + i];
}
}
@ -207,6 +196,9 @@ static void mcf5208evb_init(ram_addr_t ram_size,
uint64_t elf_entry;
target_phys_addr_t entry;
qemu_irq *pic;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *sram = g_new(MemoryRegion, 1);
if (!cpu_model)
cpu_model = "m5208";
@ -221,12 +213,12 @@ static void mcf5208evb_init(ram_addr_t ram_size,
/* TODO: Configure BARs. */
/* DRAM at 0x40000000 */
cpu_register_physical_memory(0x40000000, ram_size,
qemu_ram_alloc(NULL, "mcf5208.ram", ram_size) | IO_MEM_RAM);
memory_region_init_ram(ram, NULL, "mcf5208.ram", ram_size);
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
/* Internal SRAM. */
cpu_register_physical_memory(0x80000000, 16384,
qemu_ram_alloc(NULL, "mcf5208.sram", 16384) | IO_MEM_RAM);
memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384);
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
/* Internal peripherals. */
pic = mcf_intc_init(0xfc048000, env);
@ -235,7 +227,7 @@ static void mcf5208evb_init(ram_addr_t ram_size,
mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]);
mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]);
mcf5208_sys_init(pic);
mcf5208_sys_init(address_space_mem, pic);
if (nb_nics > 1) {
fprintf(stderr, "Too many NICs\n");

43
hw/milkymist-minimac2.c
View File

@ -97,6 +97,8 @@ struct MilkymistMinimac2State {
NICConf conf;
char *phy_model;
target_phys_addr_t buffers_base;
MemoryRegion buffers;
MemoryRegion regs_region;
qemu_irq rx_irq;
qemu_irq tx_irq;
@ -320,8 +322,8 @@ static ssize_t minimac2_rx(VLANClientState *nc, const uint8_t *buf, size_t size)
return size;
}
static uint32_t
minimac2_read(void *opaque, target_phys_addr_t addr)
static uint64_t
minimac2_read(void *opaque, target_phys_addr_t addr, unsigned size)
{
MilkymistMinimac2State *s = opaque;
uint32_t r = 0;
@ -350,7 +352,8 @@ minimac2_read(void *opaque, target_phys_addr_t addr)
}
static void
minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
minimac2_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
MilkymistMinimac2State *s = opaque;
@ -395,16 +398,14 @@ minimac2_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const minimac2_read_fn[] = {
NULL,
NULL,
&minimac2_read,
};
static CPUWriteMemoryFunc * const minimac2_write_fn[] = {
NULL,
NULL,
&minimac2_write,
static const MemoryRegionOps minimac2_ops = {
.read = minimac2_read,
.write = minimac2_write,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static int minimac2_can_rx(VLANClientState *nc)
@ -457,25 +458,23 @@ static NetClientInfo net_milkymist_minimac2_info = {
static int milkymist_minimac2_init(SysBusDevice *dev)
{
MilkymistMinimac2State *s = FROM_SYSBUS(typeof(*s), dev);
int regs;
ram_addr_t buffers;
size_t buffers_size = TARGET_PAGE_ALIGN(3 * MINIMAC2_BUFFER_SIZE);
sysbus_init_irq(dev, &s->rx_irq);
sysbus_init_irq(dev, &s->tx_irq);
regs = cpu_register_io_memory(minimac2_read_fn, minimac2_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, regs);
memory_region_init_io(&s->regs_region, &minimac2_ops, s,
"minimac2-mmio", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
/* register buffers memory */
buffers = qemu_ram_alloc(NULL, "milkymist_minimac2.buffers", buffers_size);
s->rx0_buf = qemu_get_ram_ptr(buffers);
memory_region_init_ram(&s->buffers, NULL, "milkymist_minimac2.buffers",
buffers_size);
s->rx0_buf = memory_region_get_ram_ptr(&s->buffers);
s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE;
s->tx_buf = s->rx1_buf + MINIMAC2_BUFFER_SIZE;
cpu_register_physical_memory(s->buffers_base, buffers_size,
buffers | IO_MEM_RAM);
sysbus_add_memory(dev, s->buffers_base, &s->buffers);
qemu_macaddr_default_if_unset(&s->conf.macaddr);
s->nic = qemu_new_nic(&net_milkymist_minimac2_info, &s->conf,

48
hw/milkymist-softusb.c
View File

@ -49,6 +49,9 @@ struct MilkymistSoftUsbState {
HIDState hid_kbd;
HIDState hid_mouse;
MemoryRegion regs_region;
MemoryRegion pmem;
MemoryRegion dmem;
qemu_irq irq;
/* device properties */
@ -68,7 +71,8 @@ struct MilkymistSoftUsbState {
};
typedef struct MilkymistSoftUsbState MilkymistSoftUsbState;
static uint32_t softusb_read(void *opaque, target_phys_addr_t addr)
static uint64_t softusb_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
uint32_t r = 0;
@ -91,7 +95,8 @@ static uint32_t softusb_read(void *opaque, target_phys_addr_t addr)
}
static void
softusb_write(void *opaque, target_phys_addr_t addr, uint32_t value)
softusb_write(void *opaque, target_phys_addr_t addr, uint64_t value,
unsigned size)
{
MilkymistSoftUsbState *s = opaque;
@ -110,16 +115,14 @@ softusb_write(void *opaque, target_phys_addr_t addr, uint32_t value)
}
}
static CPUReadMemoryFunc * const softusb_read_fn[] = {
NULL,
NULL,
&softusb_read,
};
static CPUWriteMemoryFunc * const softusb_write_fn[] = {
NULL,
NULL,
&softusb_write,
static const MemoryRegionOps softusb_mmio_ops = {
.read = softusb_read,
.write = softusb_write,
.endianness = DEVICE_NATIVE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
};
static inline void softusb_read_dmem(MilkymistSoftUsbState *s,
@ -256,23 +259,20 @@ static void milkymist_softusb_reset(DeviceState *d)
static int milkymist_softusb_init(SysBusDevice *dev)
{
MilkymistSoftUsbState *s = FROM_SYSBUS(typeof(*s), dev);
int softusb_regs;
ram_addr_t pmem_ram;
ram_addr_t dmem_ram;
sysbus_init_irq(dev, &s->irq);
softusb_regs = cpu_register_io_memory(softusb_read_fn, softusb_write_fn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, R_MAX * 4, softusb_regs);
memory_region_init_io(&s->regs_region, &softusb_mmio_ops, s,
"milkymist-softusb", R_MAX * 4);
sysbus_init_mmio_region(dev, &s->regs_region);
/* register pmem and dmem */
pmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.pmem", s->pmem_size);
cpu_register_physical_memory(s->pmem_base, s->pmem_size,
pmem_ram | IO_MEM_RAM);
dmem_ram = qemu_ram_alloc(NULL, "milkymist_softusb.dmem", s->dmem_size);
cpu_register_physical_memory(s->dmem_base, s->dmem_size,
dmem_ram | IO_MEM_RAM);
memory_region_init_ram(&s->pmem, NULL, "milkymist_softusb.pmem",
s->pmem_size);
sysbus_add_memory(dev, s->pmem_base, &s->pmem);
memory_region_init_ram(&s->dmem, NULL, "milkymist_softusb.dmem",
s->dmem_size);
sysbus_add_memory(dev, s->dmem_base, &s->dmem);
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain);

13
hw/milkymist.c
View File

@ -29,6 +29,7 @@
#include "blockdev.h"
#include "milkymist-hw.h"
#include "lm32.h"
#include "exec-memory.h"
#define BIOS_FILENAME "mmone-bios.bin"
#define BIOS_OFFSET 0x00860000
@ -81,8 +82,8 @@ milkymist_init(ram_addr_t ram_size_not_used,
CPUState *env;
int kernel_size;
DriveInfo *dinfo;
ram_addr_t phys_sdram;
ram_addr_t phys_flash;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *phys_sdram = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq;
int i;
char *bios_filename;
@ -109,14 +110,12 @@ milkymist_init(ram_addr_t ram_size_not_used,
cpu_lm32_set_phys_msb_ignore(env, 1);
phys_sdram = qemu_ram_alloc(NULL, "milkymist.sdram", sdram_size);
cpu_register_physical_memory(sdram_base, sdram_size,
phys_sdram | IO_MEM_RAM);
memory_region_init_ram(phys_sdram, NULL, "milkymist.sdram", sdram_size);
memory_region_add_subregion(address_space_mem, sdram_base, phys_sdram);
phys_flash = qemu_ram_alloc(NULL, "milkymist.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* Numonyx JS28F256J3F105 */
pflash_cfi01_register(flash_base, phys_flash,
pflash_cfi01_register(flash_base, NULL, "milkymist.flash", flash_size,
dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 2,
0x00, 0x89, 0x00, 0x1d, 1);

17
hw/mips_fulong2e.c
View File

@ -38,6 +38,7 @@
#include "vt82c686.h"
#include "mc146818rtc.h"
#include "blockdev.h"
#include "exec-memory.h"
#define DEBUG_FULONG2E_INIT
@ -256,7 +257,9 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
unsigned long ram_offset, bios_offset;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *ram = g_new(MemoryRegion, 1);
MemoryRegion *bios = g_new(MemoryRegion, 1);
long bios_size;
int64_t kernel_entry;
qemu_irq *i8259;
@ -288,12 +291,12 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
bios_size = 1024 * 1024;
/* allocate RAM */
ram_offset = qemu_ram_alloc(NULL, "fulong2e.ram", ram_size);
bios_offset = qemu_ram_alloc(NULL, "fulong2e.bios", bios_size);
memory_region_init_ram(ram, NULL, "fulong2e.ram", ram_size);
memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size);
memory_region_set_readonly(bios, true);
cpu_register_physical_memory(0, ram_size, ram_offset);
cpu_register_physical_memory(0x1fc00000LL,
bios_size, bios_offset | IO_MEM_ROM);
memory_region_add_subregion(address_space_mem, 0, ram);
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/* We do not support flash operation, just loading pmon.bin as raw BIOS.
* Please use -L to set the BIOS path and -bios to set bios name. */
@ -304,7 +307,7 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device,
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel (env);
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
if (bios_name == NULL) {
bios_name = FULONG_BIOSNAME;

54
hw/mips_malta.c
View File

@ -46,6 +46,7 @@
#include "elf.h"
#include "mc146818rtc.h"
#include "blockdev.h"
#include "exec-memory.h"
//#define DEBUG_BOARD_INIT
@ -769,8 +770,10 @@ void mips_malta_init (ram_addr_t ram_size,
const char *initrd_filename, const char *cpu_model)
{
char *filename;
pflash_t *fl;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *bios, *bios_alias = g_new(MemoryRegion, 1);
target_long bios_size;
int64_t kernel_entry;
PCIBus *pci_bus;
@ -826,17 +829,9 @@ void mips_malta_init (ram_addr_t ram_size,
exit(1);
}
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Map the bios at two physical locations, as on the real board. */
cpu_register_physical_memory(0x1e000000LL,
BIOS_SIZE, bios_offset | IO_MEM_ROM);
cpu_register_physical_memory(0x1fc00000LL,
BIOS_SIZE, bios_offset | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
@ -848,12 +843,19 @@ void mips_malta_init (ram_addr_t ram_size,
/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
if (kernel_filename) {
/* Write a small bootloader to the flash location. */
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios_alias, "bios.1fc", bios, 0, BIOS_SIZE);
/* Map the bios at two physical locations, as on the real board. */
memory_region_add_subregion(system_memory, 0x1e000000LL, bios);
memory_region_add_subregion(system_memory, 0x1fc00000LL, bios_alias);
loaderparams.ram_size = ram_size;
loaderparams.kernel_filename = kernel_filename;
loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel();
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry);
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
@ -862,15 +864,31 @@ void mips_malta_init (ram_addr_t ram_size,
fl_sectors = bios_size >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " TARGET_FMT_lx " at "
"offset %08lx addr %08llx '%s' %x\n",
fl_idx, bios_size, bios_offset, 0x1e000000LL,
"addr %08llx '%s' %x\n",
fl_idx, bios_size, 0x1e000000LL,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
pflash_cfi01_register(0x1e000000LL, bios_offset,
dinfo->bdrv, 65536, fl_sectors,
4, 0x0000, 0x0000, 0x0000, 0x0000, be);
fl_idx++;
fl = pflash_cfi01_register(0x1e000000LL,
NULL, "mips_malta.bios", BIOS_SIZE,
dinfo->bdrv, 65536, fl_sectors,
4, 0x0000, 0x0000, 0x0000, 0x0000, be);
bios = pflash_cfi01_get_memory(fl);
/* Map the bios at two physical locations, as on the real board. */
memory_region_init_alias(bios_alias, "bios.1fc",
bios, 0, BIOS_SIZE);
memory_region_add_subregion(system_memory, 0x1fc00000LL,
bios_alias);
fl_idx++;
} else {
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "mips_malta.bios", BIOS_SIZE);
memory_region_set_readonly(bios, true);
memory_region_init_alias(bios_alias, "bios.1fc",
bios, 0, BIOS_SIZE);
/* Map the bios at two physical locations, as on the real board. */
memory_region_add_subregion(system_memory, 0x1e000000LL, bios);
memory_region_add_subregion(system_memory, 0x1fc00000LL,
bios_alias);
/* Load a BIOS image. */
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
@ -893,7 +911,7 @@ void mips_malta_init (ram_addr_t ram_size,
a neat trick which allows bi-endian firmware. */
#ifndef TARGET_WORDS_BIGENDIAN
{
uint32_t *addr = qemu_get_ram_ptr(bios_offset);;
uint32_t *addr = memory_region_get_ram_ptr(bios);
uint32_t *end = addr + bios_size;
while (addr < end) {
bswap32s(addr);
@ -905,7 +923,7 @@ void mips_malta_init (ram_addr_t ram_size,
/* Board ID = 0x420 (Malta Board with CoreLV)
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
map to the board ID. */
stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420);
stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
/* Init internal devices */
cpu_mips_irq_init_cpu(env);

13
hw/mips_r4k.c
View File

@ -23,6 +23,7 @@
#include "elf.h"
#include "mc146818rtc.h"
#include "blockdev.h"
#include "exec-memory.h"
#define MAX_IDE_BUS 2
@ -163,7 +164,7 @@ void mips_r4k_init (ram_addr_t ram_size,
{
char *filename;
ram_addr_t ram_offset;
ram_addr_t bios_offset;
MemoryRegion *bios;
int bios_size;
CPUState *env;
ResetData *reset_info;
@ -227,15 +228,15 @@ void mips_r4k_init (ram_addr_t ram_size,
be = 0;
#endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
bios_offset | IO_MEM_ROM);
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
uint32_t mips_rom = 0x00400000;
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom);
if (!pflash_cfi01_register(0x1fc00000, bios_offset,
if (!pflash_cfi01_register(0x1fc00000, NULL, "mips_r4k.bios", mips_rom,
dinfo->bdrv, sector_len,
mips_rom / sector_len,
4, 0, 0, 0, 0, be)) {

8
hw/musicpal.c
View File

@ -1565,16 +1565,16 @@ static void musicpal_init(ram_addr_t ram_size,
* image is smaller than 32 MB.
*/
#ifdef TARGET_WORDS_BIGENDIAN
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
"musicpal.flash", flash_size),
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
"musicpal.flash", flash_size,
dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 1);
#else
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL,
"musicpal.flash", flash_size),
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, NULL,
"musicpal.flash", flash_size,
dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size,

8
hw/omap_sx1.c
View File

@ -161,8 +161,8 @@ static void sx1_init(ram_addr_t ram_size,
#endif
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(NULL,
"omap_sx1.flash0-1", flash_size),
if (!pflash_cfi01_register(OMAP_CS0_BASE, NULL,
"omap_sx1.flash0-1", flash_size,
dinfo->bdrv, sector_size,
flash_size / sector_size,
4, 0, 0, 0, 0, be)) {
@ -182,8 +182,8 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io);
if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(NULL,
"omap_sx1.flash1-1", flash1_size),
if (!pflash_cfi01_register(OMAP_CS1_BASE, NULL,
"omap_sx1.flash1-1", flash1_size,
dinfo->bdrv, sector_size,
flash1_size / sector_size,
4, 0, 0, 0, 0, be)) {

86
hw/pci_host.c
View File

@ -94,82 +94,72 @@ uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len)
return val;
}
static void pci_host_config_write(ReadWriteHandler *handler,
pcibus_t addr, uint32_t val, int len)
static void pci_host_config_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCIHostState *s = opaque;
PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n",
__func__, addr, len, val);
s->config_reg = val;
}
static uint32_t pci_host_config_read(ReadWriteHandler *handler,
pcibus_t addr, int len)
static uint64_t pci_host_config_read(void *opaque, target_phys_addr_t addr,
unsigned len)
{
PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
PCIHostState *s = opaque;
uint32_t val = s->config_reg;
PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n",
__func__, addr, len, val);
return val;
}
static void pci_host_data_write(ReadWriteHandler *handler,
pcibus_t addr, uint32_t val, int len)
static void pci_host_data_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
addr, len, val);
PCIHostState *s = opaque;
PCI_DPRINTF("write addr " TARGET_FMT_plx " len %d val %x\n",
addr, len, (unsigned)val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, len);
}
static uint32_t pci_host_data_read(ReadWriteHandler *handler,
pcibus_t addr, int len)
static uint64_t pci_host_data_read(void *opaque,
target_phys_addr_t addr, unsigned len)
{
PCIHostState *s = container_of(handler, PCIHostState, data_handler);
PCIHostState *s = opaque;
uint32_t val;
if (!(s->config_reg & (1 << 31)))
return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n",
addr, len, val);
return val;
}
static void pci_host_init(PCIHostState *s)
{
s->conf_handler.write = pci_host_config_write;
s->conf_handler.read = pci_host_config_read;
s->data_handler.write = pci_host_data_write;
s->data_handler.read = pci_host_data_read;
}
const MemoryRegionOps pci_host_conf_le_ops = {
.read = pci_host_config_read,
.write = pci_host_config_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
int pci_host_conf_register_mmio(PCIHostState *s, int endian)
{
pci_host_init(s);
return cpu_register_io_memory_simple(&s->conf_handler, endian);
}
const MemoryRegionOps pci_host_conf_be_ops = {
.read = pci_host_config_read,
.write = pci_host_config_write,
.endianness = DEVICE_BIG_ENDIAN,
};
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
pci_host_init(s);
register_ioport_simple(&s->conf_handler, ioport, 4, 4);
sysbus_init_ioports(&s->busdev, ioport, 4);
}
const MemoryRegionOps pci_host_data_le_ops = {
.read = pci_host_data_read,
.write = pci_host_data_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
const MemoryRegionOps pci_host_data_be_ops = {
.read = pci_host_data_read,
.write = pci_host_data_write,
.endianness = DEVICE_BIG_ENDIAN,
};
int pci_host_data_register_mmio(PCIHostState *s, int endian)
{
pci_host_init(s);
return cpu_register_io_memory_simple(&s->data_handler, endian);
}
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
{
pci_host_init(s);
register_ioport_simple(&s->data_handler, ioport, 4, 1);
register_ioport_simple(&s->data_handler, ioport, 4, 2);
register_ioport_simple(&s->data_handler, ioport, 4, 4);
sysbus_init_ioports(&s->busdev, ioport, 4);
}

16
hw/pci_host.h
View File

@ -29,12 +29,11 @@
#define PCI_HOST_H
#include "sysbus.h"
#include "rwhandler.h"
struct PCIHostState {
SysBusDevice busdev;
ReadWriteHandler conf_handler;
ReadWriteHandler data_handler;
MemoryRegion conf_mem;
MemoryRegion data_mem;
MemoryRegion *address_space;
uint32_t config_reg;
PCIBus *bus;
@ -49,12 +48,9 @@ uint32_t pci_host_config_read_common(PCIDevice *pci_dev, uint32_t addr,
void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len);
uint32_t pci_data_read(PCIBus *s, uint32_t addr, int len);
/* for mmio */
int pci_host_conf_register_mmio(PCIHostState *s, int endian);
int pci_host_data_register_mmio(PCIHostState *s, int endian);
/* for ioio */
void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s);
void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s);
extern const MemoryRegionOps pci_host_conf_le_ops;
extern const MemoryRegionOps pci_host_conf_be_ops;
extern const MemoryRegionOps pci_host_data_le_ops;
extern const MemoryRegionOps pci_host_data_be_ops;
#endif /* PCI_HOST_H */

5
hw/petalogix_ml605_mmu.c
View File

@ -149,7 +149,6 @@ petalogix_ml605_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = MEMORY_BASEADDR;
ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
@ -169,11 +168,11 @@ petalogix_ml605_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "petalogix_ml605.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, phys_flash,
pflash_cfi01_register(FLASH_BASEADDR,
NULL, "petalogix_ml605.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0);

5
hw/petalogix_s3adsp1800_mmu.c
View File

@ -127,7 +127,6 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = 0x90000000;
ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq;
/* init CPUs */
@ -148,9 +147,9 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xa0000000, phys_flash,
pflash_cfi01_register(0xa0000000,
NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);

78
hw/pflash_cfi01.c
View File

@ -40,6 +40,7 @@
#include "flash.h"
#include "block.h"
#include "qemu-timer.h"
#include "exec-memory.h"
#define PFLASH_BUG(fmt, ...) \
do { \
@ -74,8 +75,7 @@ struct pflash_t {
target_phys_addr_t counter;
unsigned int writeblock_size;
QEMUTimer *timer;
ram_addr_t off;
int fl_mem;
MemoryRegion mem;
void *storage;
};
@ -89,8 +89,7 @@ static void pflash_timer (void *opaque)
if (pfl->bypass) {
pfl->wcycle = 2;
} else {
cpu_register_physical_memory(pfl->base, pfl->total_len,
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
memory_region_rom_device_set_readable(&pfl->mem, true);
pfl->wcycle = 0;
}
pfl->cmd = 0;
@ -263,7 +262,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
if (!pfl->wcycle) {
/* Set the device in I/O access mode */
cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem);
memory_region_rom_device_set_readable(&pfl->mem, false);
}
switch (pfl->wcycle) {
@ -422,8 +421,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
__func__, offset, pfl->wcycle, pfl->cmd, value);
reset_flash:
cpu_register_physical_memory(pfl->base, pfl->total_len,
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
memory_region_rom_device_set_readable(&pfl->mem, true);
pfl->bypass = 0;
pfl->wcycle = 0;
@ -514,28 +512,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0);
}
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
&pflash_writeb_be,
&pflash_writew_be,
&pflash_writel_be,
static const MemoryRegionOps pflash_cfi01_ops_be = {
.old_mmio = {
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
&pflash_readb_be,
&pflash_readw_be,
&pflash_readl_be,
};
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
static const MemoryRegionOps pflash_cfi01_ops_le = {
.old_mmio = {
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* Count trailing zeroes of a 32 bits quantity */
@ -574,12 +564,13 @@ static int ctz32 (uint32_t n)
return ret;
}
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pflash_t *pflash_cfi01_register(target_phys_addr_t base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width,
uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3,
int be)
uint16_t id2, uint16_t id3, int be)
{
pflash_t *pfl;
target_phys_addr_t total_len;
@ -596,27 +587,19 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be, pfl,
DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le, pfl,
DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,
off | pfl->fl_mem | IO_MEM_ROMD);
memory_region_init_rom_device(
&pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl,
qdev, name, size);
pfl->storage = memory_region_get_ram_ptr(&pfl->mem);
memory_region_add_subregion(get_system_memory(), base, &pfl->mem);
pfl->bs = bs;
if (pfl->bs) {
/* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
if (ret < 0) {
cpu_unregister_io_memory(pfl->fl_mem);
memory_region_del_subregion(get_system_memory(), &pfl->mem);
memory_region_destroy(&pfl->mem);
g_free(pfl);
return NULL;
}
@ -724,3 +707,8 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
return pfl;
}
MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl)
{
return &fl->mem;
}

95
hw/pflash_cfi02.c
View File

@ -39,6 +39,7 @@
#include "flash.h"
#include "qemu-timer.h"
#include "block.h"
#include "exec-memory.h"
//#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG
@ -69,25 +70,38 @@ struct pflash_t {
uint8_t cfi_len;
uint8_t cfi_table[0x52];
QEMUTimer *timer;
ram_addr_t off;
int fl_mem;
/* The device replicates the flash memory across its memory space. Emulate
* that by having a container (.mem) filled with an array of aliases
* (.mem_mappings) pointing to the flash memory (.orig_mem).
*/
MemoryRegion mem;
MemoryRegion *mem_mappings; /* array; one per mapping */
MemoryRegion orig_mem;
int rom_mode;
int read_counter; /* used for lazy switch-back to rom mode */
void *storage;
};
/*
* Set up replicated mappings of the same region.
*/
static void pflash_setup_mappings(pflash_t *pfl)
{
unsigned i;
target_phys_addr_t size = memory_region_size(&pfl->orig_mem);
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
for (i = 0; i < pfl->mappings; ++i) {
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias",
&pfl->orig_mem, 0, size);
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
}
}
static void pflash_register_memory(pflash_t *pfl, int rom_mode)
{
unsigned long phys_offset = pfl->fl_mem;
int i;
if (rom_mode)
phys_offset |= pfl->off | IO_MEM_ROMD;
pfl->rom_mode = rom_mode;
for (i = 0; i < pfl->mappings; i++)
cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
pfl->chip_len, phys_offset);
memory_region_rom_device_set_readable(&pfl->orig_mem, rom_mode);
}
static void pflash_timer (void *opaque)
@ -538,28 +552,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0);
}
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = {
&pflash_writeb_be,
&pflash_writew_be,
&pflash_writel_be,
static const MemoryRegionOps pflash_cfi02_ops_be = {
.old_mmio = {
.read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
.write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUReadMemoryFunc * const pflash_read_ops_be[] = {
&pflash_readb_be,
&pflash_readw_be,
&pflash_readl_be,
};
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
static const MemoryRegionOps pflash_cfi02_ops_le = {
.old_mmio = {
.read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
.write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
};
/* Count trailing zeroes of a 32 bits quantity */
@ -598,7 +604,9 @@ static int ctz32 (uint32_t n)
return ret;
}
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
pflash_t *pflash_cfi02_register(target_phys_addr_t base,
DeviceState *qdev, const char *name,
target_phys_addr_t size,
BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1,
@ -618,32 +626,25 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
return NULL;
#endif
pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be,
pfl, DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le,
pfl, DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
memory_region_init_rom_device(
&pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl,
qdev, name, size);
pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem);
pfl->base = base;
pfl->chip_len = chip_len;
pfl->mappings = nb_mappings;
pflash_register_memory(pfl, 1);
pfl->bs = bs;
if (pfl->bs) {
/* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
if (ret < 0) {
cpu_unregister_io_memory(pfl->fl_mem);
g_free(pfl);
return NULL;
}
}
pflash_setup_mappings(pfl);
pfl->rom_mode = 1;
memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
#if 0 /* XXX: there should be a bit to set up read-only,
* the same way the hardware does (with WP pin).
*/

13
hw/piix_pci.c
View File

@ -142,6 +142,7 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
int i, r;
uint32_t smram;
memory_region_transaction_begin();
update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3,
&d->pam_regions[0]);
for(i = 0; i < 12; i++) {
@ -162,6 +163,7 @@ static void i440fx_update_memory_mappings(PCII440FXState *d)
d->smram_enabled = false;
}
}
memory_region_transaction_commit();
}
static void i440fx_set_smm(int val, void *arg)
@ -235,9 +237,16 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
{
I440FXState *s = FROM_SYSBUS(I440FXState, dev);
pci_host_conf_register_ioport(0xcf8, s);
memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
"pci-conf-idx", 4);
sysbus_add_io(dev, 0xcf8, &s->conf_mem);
sysbus_init_ioports(&s->busdev, 0xcf8, 4);
memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
"pci-conf-data", 4);
sysbus_add_io(dev, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
pci_host_data_register_ioport(0xcfc, s);
return 0;
}

49
hw/ppc405_boards.c
View File

@ -32,6 +32,7 @@
#include "qemu-log.h"
#include "loader.h"
#include "blockdev.h"
#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024)
@ -181,7 +182,8 @@ static void ref405ep_init (ram_addr_t ram_size,
ppc4xx_bd_info_t bd;
CPUPPCState *env;
qemu_irq *pic;
ram_addr_t sram_offset, bios_offset, bdloc;
MemoryRegion *bios;
ram_addr_t sram_offset, bdloc;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size;
@ -224,15 +226,15 @@ static void ref405ep_init (ram_addr_t ram_size,
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv);
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
" at offset %08lx addr %lx '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
" at addr %lx '%s' %d\n",
fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
pflash_cfi02_register((uint32_t)(-bios_size),
NULL, "ef405ep.bios", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);
@ -243,12 +245,13 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n");
#endif
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@ -259,8 +262,9 @@ static void ref405ep_init (ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(),
(uint32_t)(-bios_size), bios);
}
/* Register FPGA */
#ifdef DEBUG_BOARD_INIT
@ -507,7 +511,7 @@ static void taihu_405ep_init(ram_addr_t ram_size,
{
char *filename;
qemu_irq *pic;
ram_addr_t bios_offset;
MemoryRegion *bios;
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size;
@ -544,14 +548,14 @@ static void taihu_405ep_init(ram_addr_t ram_size,
/* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16;
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
" at offset %08lx addr %lx '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size,
" at addr %lx '%s' %d\n",
fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
pflash_cfi02_register((uint32_t)(-bios_size),
NULL, "taihu_405ep.bios", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);
@ -564,10 +568,11 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#endif
if (bios_name == NULL)
bios_name = BIOS_FILENAME;
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
bios = g_new(MemoryRegion, 1);
memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename);
} else {
bios_size = -1;
@ -578,8 +583,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
exit(1);
}
bios_size = (bios_size + 0xfff) & ~0xfff;
cpu_register_physical_memory((uint32_t)(-bios_size),
bios_size, bios_offset | IO_MEM_ROM);
memory_region_set_readonly(bios, true);
memory_region_add_subregion(get_system_memory(), (uint32_t)(-bios_size),
bios);
}
/* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@ -590,12 +596,11 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx"
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
" at addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv));
#endif
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
pflash_cfi02_register(0xfc000000, bios_offset,
pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
1);

10
hw/ppc4xx_pci.c
View File

@ -368,10 +368,12 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
/* CFGDATA */
index = pci_host_data_register_mmio(&controller->pci_state, 1);
if (index < 0)
goto free;
cpu_register_physical_memory(config_space + PCIC0_CFGDATA, 4, index);
memory_region_init_io(&controller->pci_state.data_mem,
&pci_host_data_be_ops,
&controller->pci_state, "pci-conf-data", 4);
memory_region_add_subregion(get_system_memory(),
config_space + PCIC0_CFGDATA,
&controller->pci_state.data_mem);
/* Internal registers */
index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,

21
hw/ppce500_pci.c
View File

@ -79,8 +79,6 @@ struct PPCE500PCIState {
uint32_t gasket_time;
qemu_irq irq[4];
/* mmio maps */
int cfgaddr;
int cfgdata;
int reg;
};
@ -268,18 +266,18 @@ static void e500_pci_map(SysBusDevice *dev, target_phys_addr_t base)
PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
PPCE500PCIState *s = DO_UPCAST(PPCE500PCIState, pci_state, h);
cpu_register_physical_memory(base + PCIE500_CFGADDR, 4, s->cfgaddr);
cpu_register_physical_memory(base + PCIE500_CFGDATA, 4, s->cfgdata);
sysbus_add_memory(dev, base + PCIE500_CFGADDR, &h->conf_mem);
sysbus_add_memory(dev, base + PCIE500_CFGDATA, &h->data_mem);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
s->reg);
}
static void e500_pci_unmap(SysBusDevice *dev, target_phys_addr_t base)
{
cpu_register_physical_memory(base + PCIE500_CFGADDR, 4,
IO_MEM_UNASSIGNED);
cpu_register_physical_memory(base + PCIE500_CFGDATA, 4,
IO_MEM_UNASSIGNED);
PCIHostState *h = FROM_SYSBUS(PCIHostState, sysbus_from_qdev(dev));
sysbus_del_memory(dev, &h->conf_mem);
sysbus_del_memory(dev, &h->data_mem);
cpu_register_physical_memory(base + PCIE500_REG_BASE, PCIE500_REG_SIZE,
IO_MEM_UNASSIGNED);
}
@ -309,9 +307,10 @@ static int e500_pcihost_initfn(SysBusDevice *dev)
pci_create_simple(b, 0, "e500-host-bridge");
s->cfgaddr = pci_host_conf_register_mmio(&s->pci_state, DEVICE_BIG_ENDIAN);
s->cfgdata = pci_host_data_register_mmio(&s->pci_state,
DEVICE_LITTLE_ENDIAN);
memory_region_init_io(&h->conf_mem, &pci_host_conf_be_ops, h,
"pci-conf-idx", 4);
memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h,
"pci-conf-data", 4);
s->reg = cpu_register_io_memory(e500_pci_reg_read, e500_pci_reg_write, s,
DEVICE_BIG_ENDIAN);
sysbus_init_mmio_cb2(dev, e500_pci_map, e500_pci_unmap);

10
hw/prep_pci.c
View File

@ -125,9 +125,15 @@ PCIBus *pci_prep_init(qemu_irq *pic,
address_space_io,
0, 4);
pci_host_conf_register_ioport(0xcf8, s);
memory_region_init_io(&s->conf_mem, &pci_host_conf_be_ops, s,
"pci-conf-idx", 1);
memory_region_add_subregion(address_space_io, 0xcf8, &s->conf_mem);
sysbus_init_ioports(&s->busdev, 0xcf8, 1);
pci_host_data_register_ioport(0xcfc, s);
memory_region_init_io(&s->conf_mem, &pci_host_data_be_ops, s,
"pci-conf-data", 1);
memory_region_add_subregion(address_space_io, 0xcfc, &s->data_mem);
sysbus_init_ioports(&s->busdev, 0xcfc, 1);
PPC_io_memory = cpu_register_io_memory(PPC_PCIIO_read,
PPC_PCIIO_write, s,

2
hw/r2d.c
View File

@ -267,7 +267,7 @@ static void r2d_init(ram_addr_t ram_size,
/* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE),
pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (16 * 1024),
FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000,

5
hw/stellaris.c
View File

@ -15,6 +15,7 @@
#include "i2c.h"
#include "net.h"
#include "boards.h"
#include "exec-memory.h"
#define GPIO_A 0
#define GPIO_B 1
@ -1260,6 +1261,7 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
0x40024000, 0x40025000, 0x40026000};
static const int gpio_irq[7] = {0, 1, 2, 3, 4, 30, 31};
MemoryRegion *address_space_mem = get_system_memory();
qemu_irq *pic;
DeviceState *gpio_dev[7];
qemu_irq gpio_in[7][8];
@ -1274,7 +1276,8 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model,
flash_size = ((board->dc0 & 0xffff) + 1) << 1;
sram_size = (board->dc0 >> 18) + 1;
pic = armv7m_init(flash_size, sram_size, kernel_filename, cpu_model);
pic = armv7m_init(address_space_mem,
flash_size, sram_size, kernel_filename, cpu_model);
if (board->dc1 & (1 << 16)) {
dev = sysbus_create_varargs("stellaris-adc", 0x40038000,

29
hw/stellaris_enet.c
View File

@ -69,7 +69,7 @@ typedef struct {
NICState *nic;
NICConf conf;
qemu_irq irq;
int mmio_index;
MemoryRegion mmio;
} stellaris_enet_state;
static void stellaris_enet_update(stellaris_enet_state *s)
@ -130,7 +130,8 @@ static int stellaris_enet_can_receive(VLANClientState *nc)
return (s->np < 31);
}
static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
static uint64_t stellaris_enet_read(void *opaque, target_phys_addr_t offset,
unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
uint32_t val;
@ -198,7 +199,7 @@ static uint32_t stellaris_enet_read(void *opaque, target_phys_addr_t offset)
}
static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
uint32_t value)
uint64_t value, unsigned size)
{
stellaris_enet_state *s = (stellaris_enet_state *)opaque;
@ -303,17 +304,12 @@ static void stellaris_enet_write(void *opaque, target_phys_addr_t offset,
}
}
static CPUReadMemoryFunc * const stellaris_enet_readfn[] = {
stellaris_enet_read,
stellaris_enet_read,
stellaris_enet_read
static const MemoryRegionOps stellaris_enet_ops = {
.read = stellaris_enet_read,
.write = stellaris_enet_write,
.endianness = DEVICE_NATIVE_ENDIAN,
};
static CPUWriteMemoryFunc * const stellaris_enet_writefn[] = {
stellaris_enet_write,
stellaris_enet_write,
stellaris_enet_write
};
static void stellaris_enet_reset(stellaris_enet_state *s)
{
s->mdv = 0x80;
@ -391,7 +387,7 @@ static void stellaris_enet_cleanup(VLANClientState *nc)
unregister_savevm(&s->busdev.qdev, "stellaris_enet", s);
cpu_unregister_io_memory(s->mmio_index);
memory_region_destroy(&s->mmio);
g_free(s);
}
@ -408,10 +404,9 @@ static int stellaris_enet_init(SysBusDevice *dev)
{
stellaris_enet_state *s = FROM_SYSBUS(stellaris_enet_state, dev);
s->mmio_index = cpu_register_io_memory(stellaris_enet_readfn,
stellaris_enet_writefn, s,
DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, s->mmio_index);
memory_region_init_io(&s->mmio, &stellaris_enet_ops, s, "stellaris_enet",
0x1000);
sysbus_init_mmio_region(dev, &s->mmio);
sysbus_init_irq(dev, &s->irq);
qemu_macaddr_default_if_unset(&s->conf.macaddr);

29
hw/sysbus.c
View File

@ -261,3 +261,32 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev)
return strdup(path);
}
void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_memory(), addr, mem);
}
void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem, unsigned priority)
{
memory_region_add_subregion_overlap(get_system_memory(), addr, mem,
priority);
}
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem)
{
memory_region_del_subregion(get_system_memory(), mem);
}
void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem)
{
memory_region_add_subregion(get_system_io(), addr, mem);
}
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem)
{
memory_region_del_subregion(get_system_io(), mem);
}

8
hw/sysbus.h
View File

@ -58,6 +58,14 @@ void sysbus_init_ioports(SysBusDevice *dev, pio_addr_t ioport, pio_addr_t size);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
void sysbus_add_memory(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
void sysbus_add_memory_overlap(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem, unsigned priority);
void sysbus_del_memory(SysBusDevice *dev, MemoryRegion *mem);
void sysbus_add_io(SysBusDevice *dev, target_phys_addr_t addr,
MemoryRegion *mem);
void sysbus_del_io(SysBusDevice *dev, MemoryRegion *mem);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,

82
hw/unin_pci.c
View File

@ -41,7 +41,6 @@ static const int unin_irq_line[] = { 0x1b, 0x1c, 0x1d, 0x1e };
typedef struct UNINState {
SysBusDevice busdev;
PCIHostState host_state;
ReadWriteHandler data_handler;
} UNINState;
static int pci_unin_map_irq(PCIDevice *pci_dev, int irq_num)
@ -100,67 +99,70 @@ static uint32_t unin_get_config_reg(uint32_t reg, uint32_t addr)
return retval;
}
static void unin_data_write(ReadWriteHandler *handler,
pcibus_t addr, uint32_t val, int len)
static void unin_data_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned len)
{
UNINState *s = container_of(handler, UNINState, data_handler);
UNIN_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
UNINState *s = opaque;
UNIN_DPRINTF("write addr %" TARGET_FMT_plx " len %d val %"PRIx64"\n",
addr, len, val);
pci_data_write(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr),
val, len);
}
static uint32_t unin_data_read(ReadWriteHandler *handler,
pcibus_t addr, int len)
static uint64_t unin_data_read(void *opaque, target_phys_addr_t addr,
unsigned len)
{
UNINState *s = container_of(handler, UNINState, data_handler);
UNINState *s = opaque;
uint32_t val;
val = pci_data_read(s->host_state.bus,
unin_get_config_reg(s->host_state.config_reg, addr),
len);
UNIN_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n", addr, len, val);
UNIN_DPRINTF("read addr %" TARGET_FMT_plx " len %d val %x\n",
addr, len, val);
return val;
}
static const MemoryRegionOps unin_data_ops = {
.read = unin_data_read,
.write = unin_data_write,
.endianness = DEVICE_LITTLE_ENDIAN,
};
static int pci_unin_main_init_device(SysBusDevice *dev)
{
UNINState *s;
int pci_mem_config, pci_mem_data;
/* Use values found on a real PowerMac */
/* Uninorth main bus */
s = FROM_SYSBUS(UNINState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
"pci-conf-data", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_unin_reset, &s->host_state);
return 0;
}
static int pci_u3_agp_init_device(SysBusDevice *dev)
{
UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth U3 AGP bus */
s = FROM_SYSBUS(UNINState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
s->data_handler.read = unin_data_read;
s->data_handler.write = unin_data_write;
pci_mem_data = cpu_register_io_memory_simple(&s->data_handler,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &unin_data_ops, s,
"pci-conf-data", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
qemu_register_reset(pci_unin_reset, &s->host_state);
@ -170,34 +172,32 @@ static int pci_u3_agp_init_device(SysBusDevice *dev)
static int pci_unin_agp_init_device(SysBusDevice *dev)
{
UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth AGP bus */
s = FROM_SYSBUS(UNINState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-conf-data", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}
static int pci_unin_internal_init_device(SysBusDevice *dev)
{
UNINState *s;
int pci_mem_config, pci_mem_data;
/* Uninorth internal bus */
s = FROM_SYSBUS(UNINState, dev);
pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
pci_mem_data = pci_host_data_register_mmio(&s->host_state,
DEVICE_LITTLE_ENDIAN);
sysbus_init_mmio(dev, 0x1000, pci_mem_config);
sysbus_init_mmio(dev, 0x1000, pci_mem_data);
memory_region_init_io(&s->host_state.conf_mem, &pci_host_conf_le_ops,
&s->host_state, "pci-conf-idx", 0x1000);
memory_region_init_io(&s->host_state.data_mem, &pci_host_data_le_ops,
&s->host_state, "pci-conf-data", 0x1000);
sysbus_init_mmio_region(dev, &s->host_state.conf_mem);
sysbus_init_mmio_region(dev, &s->host_state.data_mem);
return 0;
}

4
hw/virtex_ml507.c
View File

@ -196,7 +196,6 @@ static void virtex_init(ram_addr_t ram_size,
target_phys_addr_t ram_base = 0;
DriveInfo *dinfo;
ram_addr_t phys_ram;
ram_addr_t phys_flash;
qemu_irq irq[32], *cpu_irq;
clk_setup_t clk_setup[7];
int kernel_size;
@ -215,9 +214,8 @@ static void virtex_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "ram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xfc000000, phys_flash,
pflash_cfi01_register(0xfc000000, NULL, "virtex.flash", FLASH_SIZE,
dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1);

2
hw/z2.c
View File

@ -305,7 +305,7 @@ static void z2_init(ram_addr_t ram_size,
}
if (!pflash_cfi01_register(Z2_FLASH_BASE,
qemu_ram_alloc(NULL, "z2.flash0", Z2_FLASH_SIZE),
NULL, "z2.flash0", Z2_FLASH_SIZE,
dinfo->bdrv, sector_len,
Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0,
be)) {

87
rwhandler.c
View File

@ -1,87 +0,0 @@
#include "rwhandler.h"
#include "ioport.h"
#include "cpu-all.h"
#define RWHANDLER_WRITE(name, len, type) \
static void name(void *opaque, type addr, uint32_t value) \
{\
struct ReadWriteHandler *handler = opaque;\
handler->write(handler, addr, value, len);\
}
#define RWHANDLER_READ(name, len, type) \
static uint32_t name(void *opaque, type addr) \
{ \
struct ReadWriteHandler *handler = opaque; \
return handler->read(handler, addr, len); \
}
RWHANDLER_WRITE(cpu_io_memory_simple_writeb, 1, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readb, 1, target_phys_addr_t);
RWHANDLER_WRITE(cpu_io_memory_simple_writew, 2, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readw, 2, target_phys_addr_t);
RWHANDLER_WRITE(cpu_io_memory_simple_writel, 4, target_phys_addr_t);
RWHANDLER_READ(cpu_io_memory_simple_readl, 4, target_phys_addr_t);
static CPUWriteMemoryFunc * const cpu_io_memory_simple_write[] = {
&cpu_io_memory_simple_writeb,
&cpu_io_memory_simple_writew,
&cpu_io_memory_simple_writel,
};
static CPUReadMemoryFunc * const cpu_io_memory_simple_read[] = {
&cpu_io_memory_simple_readb,
&cpu_io_memory_simple_readw,
&cpu_io_memory_simple_readl,
};
int cpu_register_io_memory_simple(struct ReadWriteHandler *handler, int endian)
{
if (!handler->read || !handler->write) {
return -1;
}
return cpu_register_io_memory(cpu_io_memory_simple_read,
cpu_io_memory_simple_write,
handler, endian);
}
RWHANDLER_WRITE(ioport_simple_writeb, 1, uint32_t);
RWHANDLER_READ(ioport_simple_readb, 1, uint32_t);
RWHANDLER_WRITE(ioport_simple_writew, 2, uint32_t);
RWHANDLER_READ(ioport_simple_readw, 2, uint32_t);
RWHANDLER_WRITE(ioport_simple_writel, 4, uint32_t);
RWHANDLER_READ(ioport_simple_readl, 4, uint32_t);
int register_ioport_simple(ReadWriteHandler* handler,
pio_addr_t start, int length, int size)
{
IOPortWriteFunc *write;
IOPortReadFunc *read;
int r;
switch (size) {
case 1:
write = ioport_simple_writeb;
read = ioport_simple_readb;
break;
case 2:
write = ioport_simple_writew;
read = ioport_simple_readw;
break;
default:
write = ioport_simple_writel;
read = ioport_simple_readl;
}
if (handler->write) {
r = register_ioport_write(start, length, size, write, handler);
if (r < 0) {
return r;
}
}
if (handler->read) {
r = register_ioport_read(start, length, size, read, handler);
if (r < 0) {
return r;
}
}
return 0;
}

27
rwhandler.h
View File

@ -1,27 +0,0 @@
#ifndef READ_WRITE_HANDLER_H
#define READ_WRITE_HANDLER_H
#include "qemu-common.h"
#include "ioport.h"
typedef struct ReadWriteHandler ReadWriteHandler;
/* len is guaranteed to be one of 1, 2 or 4, addr is guaranteed to fit in an
* appropriate type (io/memory/etc). They do not need to be range checked. */
typedef void WriteHandlerFunc(ReadWriteHandler *, pcibus_t addr,
uint32_t value, int len);
typedef uint32_t ReadHandlerFunc(ReadWriteHandler *, pcibus_t addr, int len);
struct ReadWriteHandler {
WriteHandlerFunc *write;
ReadHandlerFunc *read;
};
/* Helpers for when we want to use a single routine with length. */
/* CPU memory handler: both read and write must be present. */
int cpu_register_io_memory_simple(ReadWriteHandler *, int endian);
/* io port handler: can supply only read or write handlers. */
int register_ioport_simple(ReadWriteHandler *,
pio_addr_t start, int length, int size);
#endif