extracted generic code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@242 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
2521d69883
commit
d19893dab5
242
translate-i386.c
242
translate-i386.c
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@ -25,97 +25,13 @@
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#include <signal.h>
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#include <assert.h>
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#include "disas.h"
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#define DEBUG_DISAS
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#define IN_OP_I386
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#include "cpu-i386.h"
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#include "exec.h"
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#include "disas.h"
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/* XXX: move that elsewhere */
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
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int __op_param1, __op_param2, __op_param3;
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#ifdef USE_DIRECT_JUMP
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int __op_jmp0, __op_jmp1;
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#endif
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#ifdef __i386__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __s390__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __ia64__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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}
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#endif
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#ifdef __powerpc__
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#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long p;
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p = start & ~(MIN_CACHE_LINE_SIZE - 1);
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stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#endif
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#ifdef __alpha__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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asm ("imb");
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}
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#endif
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#ifdef __sparc__
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static void inline flush_icache_range(unsigned long start, unsigned long stop)
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{
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unsigned long p;
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p = start & ~(8UL - 1UL);
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stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
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for (; p < stop; p += 8)
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__asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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#endif
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#ifdef __arm__
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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register unsigned long _beg __asm ("a1") = start;
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register unsigned long _end __asm ("a2") = stop;
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register unsigned long _flg __asm ("a3") = 0;
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__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
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}
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#endif
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extern FILE *logfile;
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extern int loglevel;
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#define PREFIX_REPZ 0x01
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#define PREFIX_REPNZ 0x02
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@ -142,7 +58,7 @@ typedef struct DisasContext {
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int cpl;
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int iopl;
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int tf; /* TF cpu flag */
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TranslationBlock *tb;
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struct TranslationBlock *tb;
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} DisasContext;
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/* i386 arith/logic operations */
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@ -176,8 +92,7 @@ enum {
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NB_OPS,
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};
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#include "dyngen.h"
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#include "op-i386.h"
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#include "gen-op-i386.h"
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/* operand size */
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enum {
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@ -3748,61 +3663,10 @@ static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
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}
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}
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#ifdef DEBUG_DISAS
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static const char *op_str[] = {
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#define DEF(s, n, copy_size) #s,
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#include "opc-i386.h"
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#undef DEF
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};
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static uint8_t op_nb_args[] = {
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#define DEF(s, n, copy_size) n,
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#include "opc-i386.h"
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#undef DEF
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};
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static void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
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{
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const uint16_t *opc_ptr;
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const uint32_t *opparam_ptr;
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int c, n, i;
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opc_ptr = opc_buf;
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opparam_ptr = opparam_buf;
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for(;;) {
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c = *opc_ptr++;
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n = op_nb_args[c];
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fprintf(logfile, "0x%04x: %s",
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(int)(opc_ptr - opc_buf - 1), op_str[c]);
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for(i = 0; i < n; i++) {
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fprintf(logfile, " 0x%x", opparam_ptr[i]);
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}
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fprintf(logfile, "\n");
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if (c == INDEX_op_end)
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break;
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opparam_ptr += n;
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}
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}
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#endif
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/* XXX: make safe guess about sizes */
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#define MAX_OP_PER_INSTR 32
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#define OPC_BUF_SIZE 512
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#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
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static uint16_t gen_opc_buf[OPC_BUF_SIZE];
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static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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static uint32_t gen_opc_pc[OPC_BUF_SIZE];
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static uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
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basic block 'tb'. If search_pc is TRUE, also generate PC
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information for each intermediate instruction. */
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static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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{
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DisasContext dc1, *dc = &dc1;
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uint8_t *pc_ptr;
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@ -3833,7 +3697,7 @@ static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
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gen_opparam_ptr = gen_opparam_buf;
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dc->is_jmp = 0;
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dc->is_jmp = DISAS_NEXT;
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pc_ptr = pc_start;
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lj = -1;
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do {
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@ -3865,10 +3729,10 @@ static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
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(pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
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/* we must store the eflags state if it is not already done */
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if (dc->is_jmp != 3) {
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if (dc->is_jmp != DISAS_TB_JUMP) {
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if (dc->cc_op != CC_OP_DYNAMIC)
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gen_op_set_cc_op(dc->cc_op);
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if (dc->is_jmp != 1) {
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if (dc->is_jmp != DISAS_JUMP) {
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/* we add an additionnal jmp to update the simulated PC */
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gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
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}
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@ -3880,15 +3744,13 @@ static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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/* indicate that the hash table must be used to find the next TB */
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gen_op_movl_T0_0();
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}
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*gen_opc_ptr = INDEX_op_end;
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#ifdef DEBUG_DISAS
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if (loglevel) {
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fprintf(logfile, "----------------\n");
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fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
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disas(logfile, pc_start, pc_ptr - pc_start,
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dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
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disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
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fprintf(logfile, "\n");
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fprintf(logfile, "OP:\n");
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@ -3912,98 +3774,13 @@ static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
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return 0;
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}
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/* return non zero if the very first instruction is invalid so that
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the virtual CPU can trigger an exception.
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'*gen_code_size_ptr' contains the size of the generated code (host
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code).
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*/
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int cpu_x86_gen_code(TranslationBlock *tb,
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int max_code_size, int *gen_code_size_ptr)
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{
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uint8_t *gen_code_buf;
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int gen_code_size;
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if (gen_intermediate_code(tb, 0) < 0)
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return -1;
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/* generate machine code */
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tb->tb_next_offset[0] = 0xffff;
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tb->tb_next_offset[1] = 0xffff;
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gen_code_buf = tb->tc_ptr;
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gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
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#ifdef USE_DIRECT_JUMP
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tb->tb_jmp_offset,
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#else
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NULL,
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#endif
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gen_opc_buf, gen_opparam_buf);
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flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
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*gen_code_size_ptr = gen_code_size;
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#ifdef DEBUG_DISAS
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if (loglevel) {
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fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
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disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
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fprintf(logfile, "\n");
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fflush(logfile);
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}
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#endif
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return 0;
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}
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static const unsigned short opc_copy_size[] = {
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#define DEF(s, n, copy_size) copy_size,
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#include "opc-i386.h"
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#undef DEF
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};
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/* The simulated PC corresponding to
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'searched_pc' in the generated code is searched. 0 is returned if
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found. *found_pc contains the found PC.
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*/
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int cpu_x86_search_pc(TranslationBlock *tb,
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uint32_t *found_pc, unsigned long searched_pc)
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{
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int j, c;
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unsigned long tc_ptr;
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uint16_t *opc_ptr;
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if (gen_intermediate_code(tb, 1) < 0)
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return -1;
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/* find opc index corresponding to search_pc */
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tc_ptr = (unsigned long)tb->tc_ptr;
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if (searched_pc < tc_ptr)
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return -1;
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j = 0;
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opc_ptr = gen_opc_buf;
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for(;;) {
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c = *opc_ptr;
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if (c == INDEX_op_end)
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return -1;
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tc_ptr += opc_copy_size[c];
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if (searched_pc < tc_ptr)
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break;
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opc_ptr++;
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}
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j = opc_ptr - gen_opc_buf;
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/* now find start of instruction before */
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while (gen_opc_instr_start[j] == 0)
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j--;
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*found_pc = gen_opc_pc[j];
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return 0;
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}
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CPUX86State *cpu_x86_init(void)
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{
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CPUX86State *env;
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int i;
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static int inited;
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cpu_x86_tblocks_init();
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cpu_exec_init();
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env = malloc(sizeof(CPUX86State));
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if (!env)
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@ -4020,7 +3797,6 @@ CPUX86State *cpu_x86_init(void)
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if (!inited) {
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inited = 1;
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optimize_flags_init();
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page_init();
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}
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return env;
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}
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@ -0,0 +1,167 @@
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/*
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* Host code generation
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include "config.h"
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#define IN_OP_I386
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#include "cpu-" TARGET_ARCH ".h"
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#include "exec.h"
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#include "disas.h"
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enum {
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#define DEF(s, n, copy_size) INDEX_op_ ## s,
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#include "opc-" TARGET_ARCH ".h"
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#undef DEF
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NB_OPS,
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};
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#include "dyngen.h"
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#include "op-" TARGET_ARCH ".h"
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uint16_t gen_opc_buf[OPC_BUF_SIZE];
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uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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uint32_t gen_opc_pc[OPC_BUF_SIZE];
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uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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#ifdef DEBUG_DISAS
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static const char *op_str[] = {
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#define DEF(s, n, copy_size) #s,
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#include "opc-" TARGET_ARCH ".h"
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#undef DEF
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};
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static uint8_t op_nb_args[] = {
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#define DEF(s, n, copy_size) n,
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#include "opc-" TARGET_ARCH ".h"
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#undef DEF
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};
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void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
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{
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const uint16_t *opc_ptr;
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const uint32_t *opparam_ptr;
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int c, n, i;
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opc_ptr = opc_buf;
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opparam_ptr = opparam_buf;
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for(;;) {
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c = *opc_ptr++;
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n = op_nb_args[c];
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fprintf(logfile, "0x%04x: %s",
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(int)(opc_ptr - opc_buf - 1), op_str[c]);
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for(i = 0; i < n; i++) {
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fprintf(logfile, " 0x%x", opparam_ptr[i]);
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}
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fprintf(logfile, "\n");
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if (c == INDEX_op_end)
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break;
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opparam_ptr += n;
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}
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}
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#endif
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/* return non zero if the very first instruction is invalid so that
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the virtual CPU can trigger an exception.
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'*gen_code_size_ptr' contains the size of the generated code (host
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code).
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*/
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int cpu_gen_code(TranslationBlock *tb,
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int max_code_size, int *gen_code_size_ptr)
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{
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uint8_t *gen_code_buf;
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int gen_code_size;
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if (gen_intermediate_code(tb, 0) < 0)
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return -1;
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/* generate machine code */
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tb->tb_next_offset[0] = 0xffff;
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tb->tb_next_offset[1] = 0xffff;
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gen_code_buf = tb->tc_ptr;
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gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
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#ifdef USE_DIRECT_JUMP
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tb->tb_jmp_offset,
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#else
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NULL,
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#endif
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gen_opc_buf, gen_opparam_buf);
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*gen_code_size_ptr = gen_code_size;
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#ifdef DEBUG_DISAS
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if (loglevel) {
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fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
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disas(logfile, gen_code_buf, *gen_code_size_ptr, 1, 0);
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fprintf(logfile, "\n");
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fflush(logfile);
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}
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#endif
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return 0;
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}
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static const unsigned short opc_copy_size[] = {
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#define DEF(s, n, copy_size) copy_size,
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#include "opc-i386.h"
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#undef DEF
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};
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/* The simulated PC corresponding to
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'searched_pc' in the generated code is searched. 0 is returned if
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found. *found_pc contains the found PC.
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*/
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int cpu_search_pc(TranslationBlock *tb,
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uint32_t *found_pc, unsigned long searched_pc)
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{
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int j, c;
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unsigned long tc_ptr;
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uint16_t *opc_ptr;
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|
||||
if (gen_intermediate_code(tb, 1) < 0)
|
||||
return -1;
|
||||
|
||||
/* find opc index corresponding to search_pc */
|
||||
tc_ptr = (unsigned long)tb->tc_ptr;
|
||||
if (searched_pc < tc_ptr)
|
||||
return -1;
|
||||
j = 0;
|
||||
opc_ptr = gen_opc_buf;
|
||||
for(;;) {
|
||||
c = *opc_ptr;
|
||||
if (c == INDEX_op_end)
|
||||
return -1;
|
||||
tc_ptr += opc_copy_size[c];
|
||||
if (searched_pc < tc_ptr)
|
||||
break;
|
||||
opc_ptr++;
|
||||
}
|
||||
j = opc_ptr - gen_opc_buf;
|
||||
/* now find start of instruction before */
|
||||
while (gen_opc_instr_start[j] == 0)
|
||||
j--;
|
||||
*found_pc = gen_opc_pc[j];
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue