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SH4: Convert immediate loads to TCG

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5098 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-08-28 21:02:19 +00:00
parent f36672ae19
commit ccc9cc5bab
2 changed files with 4 additions and 16 deletions
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12
target-sh4/op.c
View file

@ -37,18 +37,6 @@ static inline void cond_t(int cond)
clr_t();
}
void OPPROTO op_movl_imm_T0(void)
{
T0 = (uint32_t) PARAM1;
RETURN();
}
void OPPROTO op_movl_imm_T1(void)
{
T1 = (uint32_t) PARAM1;
RETURN();
}
void OPPROTO op_cmp_eq_imm_T0(void)
{
cond_t((int32_t) T0 == (int32_t) PARAM1);

8
target-sh4/translate.c
View file

@ -337,12 +337,12 @@ void _decode_opc(DisasContext * ctx)
gen_op_movl_imm_rN(B7_0s, REG(B11_8));
return;
case 0x9000: /* mov.w @(disp,PC),Rn */
gen_op_movl_imm_T0(ctx->pc + 4 + B7_0 * 2);
tcg_gen_movi_tl(cpu_T[0], ctx->pc + 4 + B7_0 * 2);
gen_op_ldw_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
case 0xd000: /* mov.l @(disp,PC),Rn */
gen_op_movl_imm_T0((ctx->pc + 4 + B7_0 * 4) & ~3);
tcg_gen_movi_tl(cpu_T[0], (ctx->pc + 4 + B7_0 * 4) & ~3);
gen_op_ldl_T0_T0(ctx);
gen_op_movl_T0_rN(REG(B11_8));
return;
@ -1181,14 +1181,14 @@ void _decode_opc(DisasContext * ctx)
break;
case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */
if (!(ctx->fpscr & FPSCR_PR)) {
gen_op_movl_imm_T0(0);
tcg_gen_movi_tl(cpu_T[0], 0);
gen_op_fmov_T0_frN(FREG(B11_8));
return;
}
break;
case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */
if (!(ctx->fpscr & FPSCR_PR)) {
gen_op_movl_imm_T0(0x3f800000);
tcg_gen_movi_tl(cpu_T[0], 0x3f800000);
gen_op_fmov_T0_frN(FREG(B11_8));
return;
}