Some bits of Linux/MIPS host support, still segfaulty.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2771 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -181,6 +181,7 @@ BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
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endif
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ifeq ($(ARCH),mips)
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OP_CFLAGS+=-G 0 -fomit-frame-pointer -fno-delayed-branch
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ifeq ($(WORDS_BIGENDIAN),yes)
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BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
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else
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@ -189,6 +190,7 @@ endif
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endif
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ifeq ($(ARCH),mips64)
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OP_CFLAGS+=-G 0 -fomit-frame-pointer -fno-delayed-branch
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ifeq ($(WORDS_BIGENDIAN),yes)
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BASE_LDFLAGS+=-Wl,-T,$(SRC_PATH)/$(ARCH).ld
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else
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23
cpu-all.h
23
cpu-all.h
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@ -20,7 +20,7 @@
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#ifndef CPU_ALL_H
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#define CPU_ALL_H
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#if defined(__arm__) || defined(__sparc__)
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#if defined(__arm__) || defined(__sparc__) || defined(__mips__)
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#define WORDS_ALIGNED
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#endif
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@ -1022,6 +1022,27 @@ static inline int64_t cpu_get_real_ticks (void)
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return rval.i64;
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#endif
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}
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#elif defined(__mips__)
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static inline int64_t cpu_get_real_ticks(void)
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{
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#if __mips_isa_rev >= 2
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uint32_t count;
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static uint32_t cyc_per_count = 0;
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if (!cyc_per_count)
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__asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count));
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__asm__ __volatile__("rdhwr %1, $2" : "=r" (count));
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return (int64_t)(count * cyc_per_count);
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#else
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/* FIXME */
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static int64_t ticks = 0;
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return ticks++;
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#endif
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}
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#else
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/* The host CPU doesn't have an easily accessible cycle counter.
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Just return a monotonically increasing vlue. This will be totally wrong,
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18
cpu-exec.c
18
cpu-exec.c
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@ -1540,8 +1540,22 @@ int cpu_signal_handler(int host_signum, void *pinfo,
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/* XXX: compute is_write */
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is_write = 0;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write,
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&uc->uc_sigmask, puc);
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is_write, &uc->uc_sigmask, puc);
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}
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#elif defined(__mips__)
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int cpu_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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greg_t pc = uc->uc_mcontext.pc;
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int is_write;
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/* XXX: compute is_write */
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is_write = 0;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, &uc->uc_sigmask, puc);
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}
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#else
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@ -129,10 +129,15 @@ extern int printf(const char *, ...);
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#define AREG3 "r6"
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#endif
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#ifdef __mips__
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#define AREG0 "s3"
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#define AREG0 "fp"
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#define AREG1 "s0"
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#define AREG2 "s1"
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#define AREG3 "s2"
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#define AREG4 "s3"
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#define AREG5 "s4"
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#define AREG6 "s5"
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#define AREG7 "s6"
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#define AREG8 "s7"
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#endif
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#ifdef __sparc__
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#ifdef HOST_SOLARIS
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@ -280,5 +285,9 @@ extern int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3;
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#ifdef __mc68000
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#define EXIT_TB() asm volatile ("rts")
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#endif
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#ifdef __mips__
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#define EXIT_TB() asm volatile ("jr $ra")
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#define GOTO_LABEL_PARAM(n) asm volatile (".set noat; la $1, " ASM_NAME(__op_gen_label) #n "; jr $1; .set at")
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#endif
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#endif /* !defined(__DYNGEN_EXEC_H__) */
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92
dyngen.c
92
dyngen.c
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@ -117,6 +117,13 @@
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#define elf_check_arch(x) ((x) == EM_68K)
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#define ELF_USES_RELOCA
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#elif defined(HOST_MIPS)
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#define ELF_CLASS ELFCLASS32
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#define ELF_ARCH EM_MIPS
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#define elf_check_arch(x) ((x) == EM_MIPS)
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#define ELF_USES_RELOC
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#else
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#error unsupported CPU - please update the code
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#endif
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@ -1641,6 +1648,26 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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error("rts expected at the end of %s", name);
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copy_size = p - p_start;
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}
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#elif defined(HOST_MIPS)
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{
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#define INSN_RETURN 0x03e00008
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#define INSN_NOP 0x00000000
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uint8_t *p = p_end;
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if (p < (p_start + 0x8)) {
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error("empty code for %s", name);
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} else {
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uint32_t end_insn1, end_insn2;
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p -= 0x8;
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end_insn1 = get32((uint32_t *)(p + 0x0));
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end_insn2 = get32((uint32_t *)(p + 0x4));
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if (end_insn1 != INSN_RETURN && end_insn2 != INSN_NOP)
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error("jr ra not found at end of %s", name);
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}
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copy_size = p - p_start;
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}
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#else
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#error unsupported CPU
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#endif
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@ -2483,6 +2510,71 @@ void gen_code(const char *name, host_ulong offset, host_ulong size,
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}
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}
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}
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#elif defined(HOST_MIPS)
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{
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for (i = 0, rel = relocs; i < nb_relocs; i++, rel++) {
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if (rel->r_offset >= start_offset && rel->r_offset < start_offset + copy_size) {
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char name[256];
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int type;
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int addend;
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int reloc_offset;
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sym_name = strtab + symtab[ELF32_R_SYM(rel->r_info)].st_name;
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/* the compiler leave some unnecessary references to the code */
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if (sym_name[0] == '\0')
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continue;
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get_reloc_expr(name, sizeof(name), sym_name);
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type = ELF32_R_TYPE(rel->r_info);
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addend = get32((uint32_t *)(text + rel->r_offset));
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reloc_offset = rel->r_offset - start_offset;
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switch (type) {
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case R_MIPS_HI16:
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fprintf(outfile, " /* R_MIPS_HI16 RELOC, offset 0x%x, name %s */\n",
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rel->r_offset, sym_name);
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + 0x%x) = "
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"((*(uint32_t *)(gen_code_ptr + 0x%x)) "
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" & ~0xffff) "
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" | (((%s - 0x8000) >> 16) & 0xffff);\n",
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reloc_offset, reloc_offset, name);
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break;
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case R_MIPS_LO16:
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fprintf(outfile, " /* R_MIPS_LO16 RELOC, offset 0x%x, name %s */\n",
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rel->r_offset, sym_name);
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + 0x%x) = "
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"((*(uint32_t *)(gen_code_ptr + 0x%x)) "
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" & ~0xffff) "
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" | (%s & 0xffff);\n",
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reloc_offset, reloc_offset, name);
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break;
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case R_MIPS_PC16:
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fprintf(outfile, " /* R_MIPS_PC16 RELOC, offset 0x%x, name %s */\n",
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rel->r_offset, sym_name);
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + 0x%x) = "
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"(0x%x & ~0xffff) "
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"| ((0x%x + ((%s - (*(uint32_t *)(gen_code_ptr + 0x%x))) >> 2)) "
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" & 0xffff);\n",
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reloc_offset, addend, addend, name, reloc_offset);
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break;
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case R_MIPS_GOT16:
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case R_MIPS_CALL16:
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fprintf(outfile, " /* R_MIPS_GOT16 RELOC, offset 0x%x, name %s */\n",
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rel->r_offset, sym_name);
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fprintf(outfile,
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" *(uint32_t *)(gen_code_ptr + 0x%x) = "
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"((*(uint32_t *)(gen_code_ptr + 0x%x)) "
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" & ~0xffff) "
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" | (((%s - 0x8000) >> 16) & 0xffff);\n",
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reloc_offset, reloc_offset, name);
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break;
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default:
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error("unsupported MIPS relocation (%d)", type);
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}
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}
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}
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}
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#else
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#error unsupported CPU
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#endif
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8
dyngen.h
8
dyngen.h
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@ -463,3 +463,11 @@ static inline void ia64_apply_fixes (uint8_t **gen_code_pp,
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}
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#endif
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#ifdef __mips__
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#include <sys/cachectl.h>
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static inline void flush_icache_range(unsigned long start, unsigned long stop)
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{
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_flush_cache ((void *)start, stop - start, BCACHE);
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}
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#endif
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22
exec-all.h
22
exec-all.h
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@ -481,6 +481,28 @@ static inline int testandset (int *p)
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}
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#endif
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#ifdef __mips__
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static inline int testandset (int *p)
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{
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int ret;
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__asm__ __volatile__ (
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" .set push \n"
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" .set noat \n"
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" .set mips2 \n"
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"1: li $1, 1 \n"
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" ll %0, %1 \n"
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" sc $1, %1 \n"
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" bnez $1, 1b \n"
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" .set pop "
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: "=r" (ret), "+R" (*p)
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:
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: "memory");
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return ret;
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}
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#endif
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typedef int spinlock_t;
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#define SPIN_LOCK_UNLOCKED 0
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